TODO: General introduction to the project
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
SAMTEC SEAF8/SEAM8 series connector will be used which provide up to 10x50=500 pins in one connector.
Readout board connector | Carrier board connector | |
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3D model | ||
Part number | SEAF8-50-1-S-10-2-RA | SEAM8-50-S02.0-S-10-3 |
Product page | https://www.samtec.com/products/seaf8-50-1-s-10-2-ra | https://www.samtec.com/products/seam8-50-s02.0-s-10-3 |
Catalog | [online version] - [local pdf] | [online version] - [local pdf] |
Drawing | [online version] - [local pdf] | [online version] - [local pdf] |
Footprint | [online version] - [local pdf] | [online version] - [local pdf] |
STEP 3D model | SEAF8-50-1-S-10-2-RA.stp | SEAM8-50-S02.0-S-10-3.stp |
Multi-board assembly | Readout Board | ASIC Carrier Board | |
---|---|---|---|
3D view | |||
Name | ePixUHR35kfps-3x2-concept | ePixUHR35kfps-3x2-readout-board-concept | ePixUHR35kfps-3x2-ASIC-carrier-board-concept |
Altium 365 project | https://stanford-linear-accelerator-center.365.altium.com/designs/1C32F53F-0F7D-4FA6-A6A2-A68D0AD370D8 | ||
Dimensions (X x Y) | N/A | 60.54mm x 160mm | 60.54mm x 42mm |
STEP 3D model | ePixUHR35kfps-3x2-concept.step | ePixUHR35kfps-3x2-readout-board-concept-PCB.step | ePixUHR35kfps-3x2-ASIC-carrier-board-concept-PCB.step |
The ePixUHR 35 kHz ASIC is used in this project. The main properties are:
Resources:
These measurements are taken from a GDS file (ePixUHR_35kHz_APonly.gds) that was opened in KLayout.
Full matrix | Lower left corner | Lower right corner | |
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Image | |||
Measurements |
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A footprint has been created in Altium Designer for the ASIC. The sizes and measurements listed above have been used and rounded to the nearest µm.
Full matrix | Lower left corner | Lower right corner | |
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Image | |||
Measurements |
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TODO
36.49 mm x 60.54 mm
pixel / array size
arrangement 3x2, 2x2, 1x1
Link to mechanical models
Notes from beam line and design teams meetings