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Power

A GUI from Linear Technologies (now Analog Devices) called LTPowerPlanner has been used to calculate all the required currents and voltages in the system. It also calculates the estimated losses and efficiency of the system.

Board power maps

The figures below give an approximation of where the power is consumed on the readout and ASIC carrier boards. The numbers are from the LTPowerPlanner block diagram above.

FPGA

• https://www.xilinx.com/products/technology/power/xpe.html
• UltraScalePlus_XPE_2023_1_2.xlsm
  • The numbers in this spreadsheet are estimates based on the epix-uhr-dev and epix-hr-m-320k firmwares
  • Note that the majority of the power is in the GTs, which means that the logic and other components can be roughly estimated

LEAP transceivers

Running at 3.3V, see datasheet on restricted OneDrive for all values. Max power condition of 7.9 W (2.4 A @ 3.3 V) is used in the calculations below.

ASICs

• ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
• ASIC Version 1 - 2022: ePixUHR: power consumption

Power rail current draw

Using worst-case values below for conservative estimate of the currents needed for the different supplies

Different options for power components

See Power supply modules and regulators page for details on interesting power supplies and regulators.

I/O needs

The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.

GT transceiver signals

The FPGA has two types of GT quads:

• GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
  • 8 quads with 4 TX/RX in each for a total of 32 transceivers
• GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
  • 11 quads with 4 TX/RX in each for a total of 44 transceivers

LEAP transceivers

The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.

ASICs

There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.

• 6*8 = 48 RX channels
• 6*1 = 6 TX channels

This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.

Total data rates

• 6x ASICs, 8x data outputs per ASIC, up to 6 Gbit/s per data output: 6*8*6=288 Gbit/s
• 12x LEAP transceiver channels up to 25 Gbit/s:
  • 1 channel will be used for timing
  • Data rate left: 11*25=275 Gbit/s
    • 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
  • Running PGPv4 at 25 Gbit/s has not been proven yet!
    • 15 Gbit/s according to this page https://confluence.slac.stanford.edu/display/ppareg/GS-12-1396
    • Main limitation is the 64-bit data width of PGPv4 which would result in a 25000/64 ≈ 390 MHz fabric clock
    • 11*15=165 Gbit/s
    • 165/(6*8) = 3.4375 Gbit/s per ASIC in this case (+encoding)

• From FPGA to PC:

  • 168*192*12(bit)*66/64(PGP encoding) = 399168 bits/frame/ASIC
  • @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
    • 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
  • @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
    • 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)

Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:

• 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
• 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
  • 22.9/8 = 2.8625 Gbit/s per data output
  • 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate

Reverse calculation assuming the current PGPv4 running at 10 Gbit/s:

• 11 channels at 10 Gbit/s: 11*10*64/66(PGP encoding) ≈ 106.67 Gbit/s
• 6 ASICs: 106.67/6*12/14(encoding) = 15.23857143 ≈ 15.24 Gbit/s per ASIC
  • 15.24/8 = 1.905 Gbit/s per data output
  • 15.23857143e9/(168*192*12) = 39368.82913256 ≈ 39 kHz frame rate

GT reference clocks

Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.

In the table below there are the following reference clock inputs (marked with X and purple/blue):

• One for the LEAP channels for the GTY quads 0 to 2
• One for the ASIC clock channels for the GTY quads 4 and 5
• One for the ASIC data channels for the GTY quads 6 and 7
• One for the ASIC data channels for the GTH quads 0 to 4
• One for the ASIC data channels for the GTH quads 5 to 9

This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See Clocks above for more details on the system clock structure.

Summary

There is one GTY quad and one GTH quad left over.