The LINAC Locking project takes the role to synchronize the LCLS-I Master Oscillator (476MHz) frequencies used by the LCLS-I (NC) Timing System with the LCLS-II Master Oscillator (11.5MHz) frequencies used by LCLS-II (SC)Timing System.
The LINAC Locking project consists on synchronizing the frequencies of the two accelerators to the common denominator between the two MO, 71.4KHz, for this reason the reference clock frequency for LCLS-I was changed from 8.5MHz to 71.4KHz prior (2019) to this project. This common frequency, 71.4KHz, is 1/14th of 1MHz; allowing all the relative phases repeat.
The reason for this project is to provide triggers to devices on the super-conducting line that are built on normal-conducting reference frequencies.
The correction of triggers will happen in S10 where the MO for NC is located. In s10, the 2856 PLL control module can move buckets to match LCLS-I. Then feed to s2, the TPG rack L2KG02-27 and to the PCDS racks.
In LCLS-I the VMTG samples the 71.4KHz and calculates how sample the 360Hz fiducial to coincide with 71.4KHz.
In LCLS-II the TPG releases fixed rate markers as part of the timing pattern, including 71.5KHz. The TPG can ignore its sampling and use TTL input to sample in ADC firmware.
A new SIOC will be added to the Master Source to detect the bucket jumps and apply a correction.
The 119MHz and 185.7MHz will be aligned as result of this project but the 360Hz AC sampling might not be aligned. To match the AC sampling, LCLS-II will use the step down chassis.
This project is taking a staged approach, first locking the RF systems then will proceed to reconfigure the TPG to get the TTL input in and use it to sample. The TPG might need a bigger FPGA to accommodate that since the 2 optical fiber inputs are used for MPS and the timing readback.
The reason for a PEER review is to present the project as a whole:
Resources collection:
