Term | Description |
---|---|
AC | Alternate Current |
ATCA | Advanced Telecommunications Computing Architecture |
CPU | Central Processing Unit |
EPICS | Experimental Physics and Industrial Control System |
FPGA | Field Programmable Gate Array |
IOC | Input Output Controller |
LCLS | Linac Coherent Light Source |
MDL | Main Drive Line |
MO | Master Oscillator |
NC | Normal-Conducting |
RF | Radio Frequency |
RFoF | RF-over-Fiber |
SC | Super-Conducting |
SHM | Shelf Manager |
VMTG | VME-based Master Trigger Generator |
The main objective of this project is to be able to use subsystems built for the LCLS-I reference frequencies with the LCLS-II beam. The beneficiaries include XTCAV, STCAV and possibly others. In order to do that, the 476MHz Master Oscillator (MO) signal for LCLS-I should be replaced with a new 476MHz source locked to the LCLS-II Master Oscillator, with the latter operating at 1300MHz.
The requirements for this project are listed below.
In LCLS-I, the 476MHz MO provides an RF source to the timing system. This signal is combined with a 360Hz signal derived from a sequencer chassis (i.e. derives a 360Hz signal coincident with the zero crossings from the 3-phase AC power line). The 476MHz and the 360Hz signals are routed to the inputs of the VME-based Master Trigger Generator (VMTG). The VMTG samples a 71.4kHz signal (a sub-harmonic of LCLS-I & LCLS-II MO frequencies) and generates a 360Hz fiducial that is aligned with the 71.4KHz signal.
(Fiducial Generation - Borrowed from Timing for LCLS slide deck, see References section below)
The VMTG output is thus synchronized with the 476MHz MO --via the 71.4kHz RF signal-- and it triggers the fiducial generator at 360Hz. The 360Hz output of the fiducial generator is amplitude-modulated onto the original 476MHz signal (hence 2.78ms between peaks and with a 476MHz frequency) and is propagated down the Main Drive Line (MDL). The aforementioned trigger generation occurs in Sector-10 in its entirety and then it gets propagated to other sectors and buildings.
With Linac Locking, the above 476MHz LCLS-I Master Oscillator gets replaced by a new RF reference that is phase-locked to the LCLS-II Master Oscillator (located in Sector-2) and transmitted to Sector-10 via an RF-over-Fiber (RFoF) connection. Lastly, the alignment of the triggers between SC and NC timing is done in Sector-20.
Linac locking is a portion of the RF distribution network that aims to support LCLS-I timing generation and distribution. See diagram below for the big picture.
(RF Distribution Network - Borrowed from Linac Locking Review slide deck, see References section below)
As already captured in the Requirements section above, the goal is to:
As of the date this documentation was produced, the work to meet the first three requirements is almost complete and is currently undergoing verification. The fourth requirement has been deferred to be tackled at a later date.
For a better idea on how the 476MHz is generated in Sector-2, there's documentation in place that describes related IOCs and existing hardware to accomplish this. See the link below for more details.
Linac Locking - PLL SIM IOCs [sioc-sys0-ms07 & sioc-sys0-ms08]
For the transmission of the RF signal from Sector-2 to Sector-10, the reader is encouraged to refer to the documentation for the RFoF IOC.
Linac Locking - RFoF Telnet IOC [sioc-sys0-ms11]
For Trigger Alignment, see the section describing the corresponding IOC.
Linac Locking - Trigger Alignment IOC [sioc-sys0-ms12]
Timing for LCLS
Linac Locking Review