Once you have the carrier hooked up, and the detector assembled, connected to the cooling system, power and fiber optics, you can power up the detector. For carrier evaluation, you do not need to connect timing fiber optics.
Once powered up, you will see the current consumption go to 1.7Amps, then go down to ~945mAmps when the FPGA is configured. Once the ASICs are configured, the current consumption will go up to 3.2Amps if all ASICs are available.
Get the latest release software on rdsrv321 (Clean room server) as follows
Get code
ssh rdsrv321 git clone --recursive git@github.com:slaclab/epix-hr-m-320k.git -b v1.1.9
Remember to document your work for each of the carriers here. Make sure you specify the digital board used as well. The carrier identified is printed on the strong back while the digital board identifier is printed on the PCB.
This test is composed of 4 steps:
- Generate eye diagram (error scan) for each lane
- Check charge injection
- Check laser
- Check BIAS as low as -50V
Overview
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