The ePixUHR35kHz Megapixel Cameras project aims to provide modular detector blocks that can be configured into larger cameras in various structural configurations. The smallest building block is a 3x2 detector sensor module which has a total of 3*2*192*168=193536≈200k pixels. Six of these (6*193536=1161216≈1M pixels) modules are assembled together into a 1 megapixel (1M) camera as shown below to the left. Four of the 1M cameras can then be assembled together around a central beam pipe aperture to form a 4M camera shown in the middle below. The largest configuration foreseen for this project is the 16M camera that consists of 16 of the 1M camera blocks as shown below on the right.
1 megapixels (1M)
6x 3x2 sensor modules:
- 6*3*2 = 36 ASICs
- 6 readout boards:
- 6 FPGAs
- 6*12 = 72 fiber pairs
16 megapixels (16M)
16x 1M camera assemblies:
- 16*36 = 576 ASICs
- 16*6 = 96 readout boards
- 96*6 = 576 FPGAs
- 96*72 = 6912 fiber pairs
Table of contents
Useful resources
- Jira Kanban board for this project
- TID-ID Edge Computing Systems
- Presentations:
- Concept Design summary presentation (Sharepoint)
Jira tasks for the project
Design
Mechanical design
Electronics design 3x2 sensor module
The electronics for the 3x2 sensor module is split into two parts; the ASIC carrier (left in the block diagram below) and the readout board (right in the block diagram). They are electrically connected together through a right-angle connector from the Samtec SEARAY connector family, which provides a total of 500 pins for signals and power. The ASIC carrier contains the 3x2 ASICs together with the 3x2 sensor and minimal amount of other components in order to reduce the size and therefore increase the sensitive area of the detector focal plane (the are which is covered by a sensitive sensor). All the active circuitry for interfacing and powering the ASICs is located on the readout board as well as the components for optical communication with the external back-end system.
Concept boards for 3x2 sensor modules
| Multi-board assembly | Readout Board | ASIC Carrier Board | |
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| 3D view |
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| Name | ePixUHR35kfps-3x2-concept | ePixUHR35kfps-3x2-readout-board-concept | ePixUHR35kfps-3x2-ASIC-carrier-board-concept |
| Overview page | |||
| Altium 365 project | https://stanford-linear-accelerator-center.365.altium.com/designs/1C32F53F-0F7D-4FA6-A6A2-A68D0AD370D8 | ||
| Dimensions (X x Y) | N/A | 60.54mm x 160mm | 60.54mm x 42mm |
| STEP 3D model | ePixUHR35kfps-3x2-concept.step | ePixUHR35kfps-3x2-readout-board-concept-PCB.step | ePixUHR35kfps-3x2-ASIC-carrier-board-concept-PCB.step |
Board-to-board connector
SAMTEC SEAF8/SEAM8 series connector will be used which provide up to 10x50=500 pins in one connector.
| Readout board connector | Carrier board connector | |
|---|---|---|
| 3D model |
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| Photo of sample |
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| Part number | SEAF8-50-1-S-10-2-RA | SEAM8-50-S02.0-S-10-3 |
| Product page | https://www.samtec.com/products/seaf8-50-1-s-10-2-ra | https://www.samtec.com/products/seam8-50-s02.0-s-10-3 |
| Catalog | [online version] - [local pdf] | [online version] - [local pdf] |
| Drawing | [online version] - [local pdf] | [online version] - [local pdf] |
| Footprint | [online version] - [local pdf] | [online version] - [local pdf] |
| STEP 3D model | SEAF8-50-1-S-10-2-RA.stp | SEAM8-50-S02.0-S-10-3.stp |
| Readout board connector | Carrier board connector | |
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| Part number | SEAF8-50-1-S-10-2-RA-GP | SEAM8-50-S02.0-S-10-3-GP |
| Product page | https://www.samtec.com/products/seaf8-50-1-s-10-2-ra-gp | https://www.samtec.com/products/seam8-50-s02.0-s-10-3-gp |
| Catalog | [online version] - [local pdf] | [online version] - [local pdf] |
| Drawing | [online version] - [local pdf] | [online version] - [local pdf] |
| Footprint | [online version] - [local pdf] | [online version] - [local pdf] |
| STEP 3D model | SEAF8-50-1-S-10-2-RA-GP.stp | SEAM8-50-S02.0-S-10-3-GP.stp |
ASIC
The ePixUHR 35 kHz ASIC is used in this project. The main properties are:
- 192 (H) x 168 (V) pixels
- 100 um x 100 um pixel size
Resources:
- Confluence page (restricted)
- iWoRiD 2023 presentation: ePixUHR-35kHz: a read-out ASIC for tender X-ray imaging at LCLS-II with 35 kHz frame-rate
Size and measurements
These measurements are taken from a GDS file (ePixUHR_35kHz_APonly.gds) that was opened in KLayout.
| Full matrix | Lower left corner | Lower right corner | |
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| Measurements |
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Altium footprint
Must be updated after changes to the ASIC
A footprint has been created in Altium Designer for the ASIC. The sizes and measurements listed above have been used and rounded to the nearest µm.
| Full matrix | Lower left corner | Lower right corner | |
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| Measurements |
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Sensor design
TODO
- Convert GDS to DXF
- Download https://www.klayout.de/, open the GDS and re-save it as DXF, done.
- Sensor first draft
36.49 mm x 60.54 mm
pixel / array size
arrangement 3x2, 2x2, 1x1
Link to mechanical models
- Dxf with the design
Block diagrams of camera configurations
These block diagrams are linked to the static .png images at the top of this page. Changing the block diagrams below will automatically update the .png images at the top.
1 megapixels (1M)
4 megapixels (4M)
16 megapixels (16M)
Not possible to replicate the original isometric view version shown below due to limitations with the Gliffy diagram tool that is used at SLAC for Confluence.
Meeting notes
- Notes from the design team meetings
Notes from beam line and design teams meetings
Overview
Content Tools