The DAQ group supports two methods of time stamping data on a user-supplied standalone detector/computer:
- For detectors running at lower rates (100Hz is a good rule-of-thumb) the DAQ group can provide access to a timing fiber and a TPR pcie board. Users would need to install the board and associated drivers on a computer they provide (only linux is supported) and write code to receive the timestamp information from the TPR card and correctly timestamp the data coming from their detector.
- For detectors running at higher rates, the time stamping of detector data typically needs to be done in firmware. The DAQ group can provide a timing fiber and direct you to open-source VHDL firmware that users can integrate into their own detector-readout FPGAs.
The data would be recorded on the user's computer, and the timestamp can be used to match the data to the DAQ data. The user will have to write the software to do the matching.
Both of these options will likely require some assistance from the DAQ group with the second option requiring more effort.
VHDL firmware for timing fiber processing
The interface module for triggering within the DAQ is https://github.com/slaclab/lcls2-pgp-fw-lib/blob/master/shared/rtl/UltraScale/TimingRx.vhd.
The most relevant ports are
| Port | Description |
|---|---|
| timingRxP : in slv(1 downto 0); timingRxN : in slv(1 downto 0); timingTxP : out slv(1 downto 0); timingTxN : out slv(1 downto 0)); | high-speed serial signals to LCLS2:LCLS1 timing |
| triggerData : out TriggerEventDataArray(NUM_DETECTORS_G-1 downto 0); | in-time trigger decisions |
| eventTrigMsgMasters : out AxiStreamMasterArray(NUM_DETECTORS_G-1 downto 0); | event header via Axi4 stream |
| eventTimingMsgMasters : out AxiStreamMasterArray(NUM_DETECTORS_G-1 downto 0); | full event timing content via Axi4 stream |
The high speed serial signals come from a GTH/GTX interface designed to operate at the 3.71 Gbps (1300MHz/7 x 20b) rate of the timing stream and 8B/10B encoding.
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