PGP version

Gen 1 hardware implements PGP version 1.

VHDL sources

PGP basics

Instantiation on RCEs

Petacache RCEs have four PGP cores named A through D while ATLAS TDAQ RCEs have three named A through C.

Core device control registers

Each PGP core has four Device Control Registers. The register base addresses are:

The individual registers for each core:

PIC block assignments

The actual PGP data transfers are scheduled and tracked through Plugin Interface Core (PIC) firmware blocks. There are at most 16 of any type of block and within each type the blocks are assigned numbers starting at zero. Each PGP core needs the use of a Pending Export Block (PEB) for the scheduling of transmissions, an Export Completion Block (ECB) to track the completion of transmissions, a Free List Block to track available buffers for reception and a Pending Import Block (PEB) to track buffers that have data from reception. Each core has its own PEB and PIB but share a common ECB and FLB. The lowest-numbered PIC blocks of each type are used for ethernet ports; one port on Petacache RCEs and two on ATLAS RCEs.

An additional PIC block called the Interrupt Summary Block tracks the state of the fault and event flags for all the other PIC blocks in the RCE.

ATLAS TDAQ RCE:

Petacahe RCE:

PIC DCR addresses

Each PIC block is assigned four consecutive DCR addresses in order by block number within type:

Software port numbers

For convenience, library and application software often refer to PGP "ports" where core A corresponds to port 0, etc. This port number is the same as the type sequence number assigned to PGP plugins by class PortList.