Software Design Documents
Hardware Design Documents
- Cluster Element Module, an I/O System On Chip
- PGP (Pretty Good Protocol)
- Register Command and Data Interface
Useful text notes for Gen1 hardware
- PIC Space Consumption txt
- PIC Exceptions and Faults txt
- Physical Layout of Lanes/FMCs/Chips on a GEN1 RCE Board txt
- Some GEN1 RCE Board Power Measurements txt
- Multifunction Display Info txt
External, Third party Documentation
RTEMS
PowerPC 405 & 440 Embedded Cores
Xilinx Virtex 4 & Virtex 5
- PowerPC Processor Reference Guide (PPC 405)
- Virtex-5 FPGA User Guide
- Virtex-5 FPGA System Monitor User Guide
- Embedded Processor Block in Virtex-5 FPGAs Reference Guide
- Virtex-5 TXT and FXT FPGA Production Errata