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The ePixUHR35kHz Megapixel Cameras project aims to provide modular detector blocks that can be configured into larger cameras in various structural configurations. The smallest building block is a 3x2 detector sensor module which has a total of 3*2*192*168=193536≈200k pixels. Six of these (6*193536=1161216≈1M pixels) modules are assembled together into a 1 megapixel (1M) camera as shown below to the left. Four of the 1M cameras can then be assembled together, around a central beam pipe aperture, to form a 4M camera shown in the middle below. The largest configuration foreseen for this project is the 16M camera that consists of 16 of the 1M camera blocks as shown below on the right.

1 megapixel (1M)

6x 3x2 sensor modules:

  • 6*3*2 = 36 ASICs
    • 36*192*168 = 1,161,216 pixels
    • 36*8 = 288 ASIC GT serial links
      • 35 kfps: 288*1.975 = 568.8 Gbit/s
  • 6 readout boards:
    • 6 FPGAs & transceivers
    • 6*12 = 72 fiber pairs
      • 72*15 = 1080 Gbit/s

4 megapixel (4M)

4x 1M camera assemblies:

  • 4*36 = 144 ASICs
    • 144*192*168 = 4,644,864 pixels
    • 144*8 = 1152 ASIC GT serial links
      • 35 kfps: 1152*1.975 = 2275.2 Gbit/s
  • 4*6 = 24 readout boards:
    • 24 FPGAs & transceivers
    • 24*12 = 288 fiber pairs
      • 288*15 = 4320 Gbit/s

16 megapixel (16M)

16x 1M camera assemblies:

  • 16*36 = 576 ASICs
    • 576*192*168 = 18,579,456 pixels
    • 576*8 = 4608 ASIC GT serial links
      • 35 kfps: 4608*1.975 = 9100.8 Gbit/s
  • 16*6 = 96 readout boards:
    • 96 FPGAs & transceivers
    • 96*12 = 1152 fiber pairs
      • 1152*15 = 17280 Gbit/s

Table of contents

Useful resources


Mechanical design

Assembly procedure

  • Bill of materials
  • Custom tools
    • These are tools developed during the design to enable insertion and extraction of the
      • 1MPix to/from 4MPix
      • 3x2 carrier modules
      • readout boards
  • Assembly procedure steps
    • Assemble 1MPix focal plane
    • Insert 1MPix focal plane into the 4Mpix cradle

1M assembly

  • The goal of this assembly is a complete 1M block
  • This involves attaching 6x of the following to the 1M cooling block
    • Carrier modules with ASICs and sensor (the most sensitive component)
    • Readout modules with cooling block attached
  • PowerPoint storyboard (work-in-progress as of 2024-05-02): LCLS-II HE Instrument - 1_4_16MPix Detector-StoryBoard.pptx

Toy model for inserting 1M module into the 4M crate


Sensor design

Due to asymmetry in the ASICs, the edges of the top row do not align exactly with the edges of the bottom row. The top row is shifted horizontally by 1.35 µm relative to the bottom row. The ASICs are spaced 19485 µm apart horizontally.


Full sensorLower left cornerBetween two ASICs at the bottomLower right cornerBetween ASICs in the middleTop left cornerTop right corner
Image

Measurements
  • Width (x): 60610 µm
  • Height (y): 36525 µm
  • x offset: 1166.695 µm
  • y offset: 502.135 µm
  • x distance: 178.74 µm
  • x offset: 1168.045 µm
  • y offset: 502.135 µm
  • x offset: 178.74 µm
  • y offset: 179.87 µm
  • x offset: 1168.045 µm
  • y offset: 502.135 µm
  • x offset: 1165.695 µm
  • y offset: 502.135 µm

Convert GDS to DXF:

Sensors for ASIC and systems characterization

There is a strong need to have sensors capable of detecting visible light during the characterization phase of the detector. This capability enables the use on lab, low power, LASER that can reproduce the fast timing and large charges that will be experienced during beam time use. X-ray sensor do have metallization in the entrance window to block visible light therefore existing sensor are not suitable

Solutions proposed 

  • Design mast on the 1x1 sensor in the production run
    • It will take more than a year to have them and adds a step in the process, which adds risks to the production run
    • Etch the metal away. Can be done in individual and prototype sensor (5x5mm)
      • Only sensor for characterization would go through this step
      • Can be done in existing sensor (have them available within a month)
      • In the past we had issues removing the metal and CK's team will investigate this since it is believe this can be consistently done
    • Decision is to make production runs with full metallization and process the sensors in house for characterization


Link to mechanical models: Dxf with the design


Electronics design for 3x2 sensor module

The electronics for the 3x2 sensor module is split into two parts; the ASIC carrier (left in the block diagram below) and the readout board (right in the block diagram). They are electrically connected together through a right-angle connector from the Samtec SEARAY connector family, which provides a total of 500 pins for signals and power. The ASIC carrier contains the 3x2 ASICs together with the 3x2 sensor and minimal amount of other components in order to reduce the size and therefore increase the sensitive area of the detector focal plane (the are which is covered by a sensitive sensor). All the active circuitry for interfacing and powering the ASICs is located on the readout board as well as the components for optical communication with the external back-end system.

More details about the electronics design for the 3x2 module can be found on a dedicated page: 3x2 Readout Overview

Gliffy Macro Error

Cannot find a diagram with these parameters:

  • Name: ePixUHR-miniTileBD

NOTE: If some of the images above are indicated as missing, please ensure that you are logged into Confluence and have access to the Board tracking pages where the images are stored.

Board-to-board connector

SAMTEC SEAF8/SEAM8 series connector will be used with 10x40=400 pins in one connector.


Readout board connectorCarrier board connector
3D model

 

Photo of sample
(50 column version)

Part numberSEAF8-40-1-S-10-2-RASEAM8-40-S02.0-S-10-3
Product pagehttps://www.samtec.com/products/seaf8-40-1-s-10-2-rahttps://www.samtec.com/products/seam8-40-s02.0-s-10-3
Catalog[online version] - [local pdf][online version] - [local pdf]
Drawing[online version] - [local pdf][online version] - [local pdf]
Footprint[online version] - [local pdf][online version] - [local pdf]
STEP 3D modelSEAF8-40-1-S-10-2-RA.stpSEAM8-40-S02.0-S-10-3.stp

50 column


Readout board connectorCarrier board connector
3D model

Photo of sample

Part numberSEAF8-50-1-S-10-2-RASEAM8-50-S02.0-S-10-3
Product pagehttps://www.samtec.com/products/seaf8-50-1-s-10-2-rahttps://www.samtec.com/products/seam8-50-s02.0-s-10-3
Catalog[online version] - [local pdf][online version] - [local pdf]
Drawing[online version] - [local pdf][online version] - [local pdf]
Footprint[online version] - [local pdf][online version] - [local pdf]
STEP 3D modelSEAF8-50-1-S-10-2-RA.stpSEAM8-50-S02.0-S-10-3.stp

50 column with guide posts


Readout board connectorCarrier board connector
3D model

Part numberSEAF8-50-1-S-10-2-RA-GPSEAM8-50-S02.0-S-10-3-GP
Product pagehttps://www.samtec.com/products/seaf8-50-1-s-10-2-ra-gphttps://www.samtec.com/products/seam8-50-s02.0-s-10-3-gp
Catalog[online version] - [local pdf][online version] - [local pdf]
Drawing[online version] - [local pdf][online version] - [local pdf]
Footprint[online version] - [local pdf][online version] - [local pdf]
STEP 3D modelSEAF8-50-1-S-10-2-RA-GP.stpSEAM8-50-S02.0-S-10-3-GP.stp

Propagation delay

Note: Due to the use of a right-angle connector there will be different path lengths for signals in different rows. See High Speed Characterization Report from Samtec.

Table 16 on page 38 shows the propagation delay of the first row A (~100 ps) to the last row K (~180 ps) for different signal configurations. These propagation delay values have been assigned to the right-angle connector footprint pads for each row and will therefore be included in the propagation delay calculation in Altium when a trace is routed.

The P and N signal of differential pairs should be placed in the same row to avoid skew between them. Timing critical signals should take into account the different propagation delays for the rows.

Propagation delays, cells with yellow color have been interpolated from the data in the report.

Row

Single-ended: 1:1 S/GSingle-ended: 2:1 S/GDifferential: Optimal HorizontalAssigned in Altium
A96 ps103 ps94 ps100 ps
B106 ps111 ps103 ps109 ps
C115 ps118 ps112 ps118 ps
D125 ps128 ps120 ps127 ps
E135 ps137 ps129 ps136 ps
F144 ps147 ps137 ps144 ps
G153 ps156 ps146 ps153 ps
H162 ps166 ps154 ps162 ps
J172 ps176 ps165 ps171 ps
K182 ps186 ps174 ps180 ps
Average difference:9.6 ps9.2 ps8.9 ps8.9 ps

Power

Power supplies

TODO, see TIDIDECS-109 - Getting issue details... STATUS

1M Power Breakout Board

  • See TIDIDECS-81 - Getting issue details... STATUS
  • The "Top" side of the board is facing the rear of the camera
  • The "Bottom" side of the board is facing the inside of the camera and connects to the six 3x2 readout boards through the TFM connectors

ASIC

The ePixUHR 100 kHz ASIC is used in this project. The main properties are:

  • 192 (H) x 168 (V) pixels
  • 100 um x 100 um pixel size
  • 8 serial data outputs operating at up to ~6 Gbit/s

Resources:

Size and measurements

These measurements are taken from a GDS file (ePixUHR_100kHz_4Julie.gds) that was opened in KLayout.


Full matrixLower left cornerLower right corner
Image

Measurements
  • Width (x): 19306.26 µm
  • Height (y): 18674.7 µm
  • Pad
    • Width (x): 60 µm
    • Height (y): 120 µm
    • Pitch: 100 µm
  • First pad location relative to lower-left corner
    • x: 573.13 µm
    • y: 45.095 µm
  • Last pad location relative to lower-right corner
    • x: 473.13 µm
    • y: 45.095 µm

A footprint has been created in Altium Designer for the ASIC. The sizes and measurements listed above have been used and rounded to the nearest µm.


Full matrixLower left cornerLower right corner
Image

Measurements
  • Width (x): 19306 µm
  • Height (y): 18674 µm
  • Pad
    • Width (x): 60 µm
    • Height (y): 120 µm
  • First pad location relative to lower-left corner
    • x: 573 µm
    • y: 45 µm
  • Last pad location relative to lower-right corner
    • x: 473 µm
    • y: 45 µm
    • Pitch: 100 µm




Block diagrams of camera configurations

The block diagrams have been created with Draw.io instead of the Gliffy integration in Confluence, which has major issue as soon as there are more than 100 items in the diagram it seems. It slows down the whole confluence page and it's near impossible to edit the diagram. There are also major limitations in the tools available in Gliffy, e.g. there doesn't seem to be a way to draw an arbitrary polygon or parallelograms.




Jira tasks for the project

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