Case for: Fast Pulse Test Board Ver00

• Fast Pulser board → PC-144-174-04-R0

Design

• Schematics [pdf][vsdx] 
  
  • Assembly
• QR Code

Fabrication and Assembly

• Assembly

  • [pdf][vsdx]

  • Expand
    title

  Assembly

  • Photos

    Image Modified Image ModifiedImage Modified Note: /\ The two 47[kOhm] resistors /\ have been replaced with x3 1/4[W] 76[kOhm] resistors (had asked for 1/2[W] for 47[kOhm], but only 1/4[W] available  Image ModifiedImage ModifiedImage Modified

• Expand
  title I/O
  CASE PCB PIN I/O Value/ Range[V] Zener to GND? Note(s)......................................................................................................................................................................... J1 1 In 0/+3.3 TTL  +3.3 Used to generate pulse J2 1 In 0 to 10 +11 Gained up by -10x to set pulse level J3 1 SPLY +15VDC +15 3 SPLY -15VDC -15 2, 4 GND GND TP1 Out 0 to -100 Ideal, really around -90V before pulse OUT Out 100 to 0 OUT: Solder pad Load with 10nF cap (CM07FD103JO3) to ground Drags out tail-end of pulse Testing done with 1[MOhm] load of scope to COMP Port 1N5624 [Digikey] in parallel with resistor to minimize negative voltage seen relative to COMP Port Note: Offset COMP +1VDC to have the diode clamp around 0V, but if COMP Port is ground, will clamp adequately to protect ASIC load

• Expand
  title Operation
  If J2 = +10VDC (effects Tp1 & OUT) ← what scales output CASE ----- PCB ----- [V] J1 PMOS Q1 [V] U1.7 TP1 OUT* Note(s) 0 ON -15 ~0 -5 ← Using fast turn on time to generate pulse +3.3 OFF +15 -90 +85 ← _TRIGGER: Normally in this state (otherwise won't work) *assumes load resistance to be negligible as it is a cap divider

Info

• SLAC SEDA