Case for: Fast Pulse Test Board Ver00

Design

Fabrication and Assembly

  • Assembly

    • [pdf][vsdx]

    • Note: /\ The two 47[kOhm] resistors /\ have been replaced with x3 1/4[W] 76[kOhm] resistors (had asked for 1/2[W] for 47[kOhm], but only 1/4[W] available 

  • CASEPCBPINI/O

    Value/

    Range[V]

    Zener

    to GND?

    Note(s).........................................................................................................................................................................


    		J11In0/+3.3 TTL +3.3Used to generate pulse

    		J21In0 to 10+11Gained up by -10x to set pulse level

    		J31SPLY+15VDC+15


    		3SPLY-15VDC-15


    		2, 4GNDGND


    		TP1
    		Out0 to -100
    		Ideal, really around -90V before pulse

    		OUT
    		Out100 to 0
    • OUT: Solder pad
      • Load with 10nF cap (CM07FD103JO3) to ground
        • Drags out tail-end of pulse
      • Testing done with 1[MOhm] load of scope to COMP Port
      • 1N5624 [Digikey] in parallel with resistor to minimize negative voltage seen relative to COMP Port
        • Note: Offset COMP +1VDC to have the diode clamp around 0V, but if COMP Port is ground, will clamp adequately to protect ASIC load

  • If J2 = +10VDC (effects Tp1 & OUT) ← what scales output

    CASE

    ----- PCB -----




    [V]

    J1

    PMOS

    Q1

    		[V]
    U1.7TP1OUT*Note(s)

    		0ON-15~0-5← Using fast turn on time to generate pulse

    		+3.3OFF+15-90+85← _TRIGGER: Normally in this state (otherwise won't work)

    *assumes load resistance to be negligible as it is a cap divider

Info

  • SLAC SEDA



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