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Computer to control the FPGA board

Vivado Lab Edition

If you don't need to compile the firmware on your own PC, you can only download the vivado lab edition for controlling FPGA. This edition is much much smaller than the full vivado software (~100GB)

https://www.xilinx.com/support/download.html

Vivado to program the FPGA

1.  connect your PC to the JTAG interface of KCU105
2. power on the board
3. start vivado
4. open hardware managerImage Added
5. open target, and choose "auto connect": Image Added
6. if it failed to see the FPGA, please check the USB cable connection, and check your PC has correctly installed the JTAG interface driver.
   1. for windows OS, the driver is always installed when you install vivado (or vivado lab edition)
   2. for linux OS, need to manually install the driver, see here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug973-vivado-release-notes-install-license.pdf#page=47

Pre-compiled firmware list

KC705, 1.25Gbps IBERT, CPLL

bit file: CPLL_example_ibert_7series_gtx_0.bit

source code:  ibert_kc705_1p25Gbps_CPLL.tar.gz

KC705, 1.25Gbps IBERT, QPLL

bit file: example_ibert_7series_gtx_0.bit

source code: ibert_7series_gtx_0_ex.tar.gz

KCU105, 1.28Gbps IBERT, QPLL (need to config the Si570 User Clock to 128MHz)

bit file: example_ibert_ultrascale_gth_0.bit

source code: ibert_ultrascale_gth_0_ex.tar.gz

KCU105, 1.5625Gbps IBERT, QPLL (with the KCU105 default clock setting)

bit file: 1p5625_example_ibert_ultrascale_gth_0.bit

source code: ibert_kcu105_speed1p56.tar.gz

KCU105, 1.25Gbps IBERT, CPLL (with the KCU105 default clock setting)

bit file: 1p25_CPLL_example_ibert_ultrascale_gth_0.bit

source code:ibert_kcu105_speed1p25_defaultClk_CPLL.tar.gz

KCU105, 1.5625Gbps IBERT, CPLL (with the KCU105 default clock setting)

bit file:1p5625_CPLL_example_ibert_ultrascale_gth_0.bit

source code:ibert_kcu105_speed1p5625_defaultClk_CPLL.tar.gz

QC of DP cables

Data transmission loss survey of miniDP cables 

miniDP-DP cable QC for QCbox R53A Ring PP0 readout