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Fast ADC for high gain (2x) channels:

Slow ADC for low gain (0.5x) channels:

  • ADC3444 Quad-Channel, 14-Bit, 125-MSPS

For the FPGA we can use a XCKU040 part for about $800

Parameters from meeting of 27 October:

Bandwidth Lower Limit = 10 kHz

Bandwidth Upper Limit = 500 MHz

Sampling Rate = 1 GHz

1 p.e. distribution probable lower limit ~ 1 mV

maximum signal = 1e4 p.e.

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