LZ Test Stand Electronics Phase 2

• Previous preamp and digitizer design:
  • PC_264_800_03_C00
  • PC_264_800_02_C00
• Gunther's presentation
• Larry's Rough Draft
• Option 1: 1-GSPS + 125-MSPS
  • Cost per PMT channel: $1,400
  • Cost per ADC channel: $700
  • Power estimate per board: 35W
• Option 2: 500-MSPS + 125-MSPS
  • Cost per PMT channel: $1,175
  • Cost per ADC channel: $590
  • Power estimate per board: 31W
• Option 3: 1-GSPS + 250-MSPS
  
  • Cost per PMT channel: $1,481
  • Cost per ADC channel: $741
  • Power estimate per board: 41W
• Option 4: 500-MSPS + 250-MSPS
  
  • Cost per PMT channel: $1,255
  • Cost per ADC channel: $628
  • Power estimate per board: 37W

Power supply design (option 3):

• Diagram
• Power estimator
• Preliminary schematics
• External power supply for one box (4 boards)
• Rack mount kit for the external power supply

Recommended ADC drivers:

• LMH3401 7-GHz, Ultra-Wideband, Fully-Differential, Fixed-Gain Amplifier (min 12dB/4x)
• LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier (-6bB/0.5x to 26dB/20x)

Driver reference designs:

• TIDUB15: 16-Bit 1-Gsps Digitizer Reference Design With AC and DC Coupled Variable Gain Amplifier
• TIDUAK3: Cascaded LMH5401 and LMH6401 Reference Design

TINA-TI simulations:

• LMH6401 AC coupled
  • Schematics for TINA-TI
• LMH6401 DC coupled
  • Schematics for TINA-TI
• Cascaded LMH5401 and LMH6401 DC coupled
  • Schematics for TINA-TI
  • Schematics in PDF
  • AC transfer in low gain (-6db/0.5x)
  • AC transfer in high gain (26db/20x)

Fast ADC for high gain (2x) channels:

• ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS
  • http://www.ti.com/lit/ds/symlink/ads54j60.pdf
  • 1.35W / channel = 10.8W for 8 high speed channels
  • Cost each = $850. Total cost for 8 channels = $3400.
  • Need 2 JESD channels per ADC, 16 total
    
    
• ADS54J54IRGCT Quad Channel, 500 MHz sampling, 14-bit
  • http://www.ti.com/lit/ds/symlink/ads54j54.pdf
  • 0.875W / channel = 7W for 8 high speed channels
  • Cost each =  $795. Total cost for 8 channels = $1590.
  • Need 2 JESD channels per ADC, 16 total

Slow ADC for low gain (0.5x) channels:

• ADS42LB69 Dual-Channel, 16-Bit, 250-MSPS
  • http://www.ti.com/lit/ds/symlink/ads42lb69.pdf
  • 0.82W / channel = 6.6W for 8 channels
  • Cost each = $240. Total cost for 8 channels =  $960
  • Uses LVDS IOs.
• ADC3444 Quad-Channel, 14-Bit, 125-MSPS
  • http://www.ti.com/lit/gpn/ADC3444
  • 0.098W / channel = ~1W for 8 channels
  • Cost each = $160. Total cost for 8 channels =  $320.
  • Uses LVDS IOs. 

For the FPGA we can use a XCKU040 part for about $800

Parameters from meeting of 27 October:

Bandwidth Lower Limit = 10 kHz

Bandwidth Upper Limit = 500 MHz

Sampling Rate = 1 GHz

1 p.e. distribution probable lower limit ~ 1 mV

maximum signal = 1e4 p.e.