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Fast Pulse Test Board Ver00

Designed by: David Brown (google drive) 

Design

Fabrication and Assembly

  • PCB Data (Pads)
  • Gerber Data (zip)
  • Assembly Drawings
  • Pick and Place Data
  • PCB 3D Top View
  • PCB 3D Bottom View

Measurement

  • Replicating @10us pulse David Brown did

    CNTRL 

    INPUTS

    INPUT

    [V]


    Units


    CONTROL+10[V]
    COMP+1.1[V]
    _TRIG+3.3 TTL[V]
    SPLY+/-15[V]

    V_OUT

    PULSE

    _TRIG

    PRD[us]


    MSRM


    Units

    Vmin
    APX +0.5[V]
    Vpp1095[V]

    195[V]

    0.2*95[V]

    0.185[V]
    Rise1091.2[ns]

    188.8[ns]

    0.2*92[ns]

    0.184[ns]
    Fall1082[us]

    152[us]

    0.2*49[us]

    0.147[us]

    *Smallest pulse = 200[nsec] without affecting Vpp

    • Found in V:\CD\David Brown\Fast Pulse
    • Found in Google-Drive:SLACers\Frisch\General\Fast Pulse
      • Believe this is OUT, R_load = 1MOhm
      • Zoom in of step


Simulation

I/O


  • PINI/O

    Value/

    Range[V]

    Zener

    to GND?

    Note(s).........................................................................................................................................................................

    J11In0/+3.3 TTL +3.3Used to generate pulse
    J21In0 to 10+11Gained up by -10x to set pulse level
    J31SPLY+15VDC+15

    3SPLY-15VDC-15

    2, 4GNDGND

    TP1
    Out0 to -100
    Ideal, really around -90V before pulse
    OUT
    Out100 to 0
    • OUT: Solder pad
      • Load with 10nF cap (CM07FD103JO3) to ground
        • Drags out tail-end of pulse
      • Testing done with 1[MOhm] load of scope to COMP Port
      • 1N5624 [Digikey] in parallel with resistor to minimize negative voltage seen relative to COMP Port
        • Note: Offset COMP +1VDC to have the diode clamp around 0V, but if COMP Port is ground, will clamp adequately to protect ASIC load

Operation

  • If J2 = +10VDC (effects Tp1 & OUT) ← what scales output

    [V]

    J1

    PMOS

    Q1

    [V]
    U1.7TP1OUT*Note(s)
    0ON-15~0-5← Using fast turn on time to generate pulse
    +3.3OFF+15-90+85← _TRIGGER: Normally in this state (otherwise won't work)

    *assumes load resistance to be negligible as it is a cap divider

Safety


Info

  • SLAC SEDA




  • Speck
    PCB IDWhatWebManualTypeMinNomMaxUnit
    U1Optocoupler

    Digi-Link

    ACNU-3430Switch Time0.2
    0.6[usec]




    VDD-VSS
    30+5
    [V]




    VSS
    -15
    [V]
    U2OPAMP

    Digi-Link

    Sply Range
    140+10
    [V]
    VR1Voltage reg.

    Digi-Link

    Sply Range
    20
    [V]
    Q1PMOS

    Digi-Link

    IXTQ36P15PSwitch Time
    0.1
    [usec]
    C10-C12Output Cap

    Digi-Link

    VJ1812Y334KXCATRating
    200
    [V]
  • Search

    • Email chain ordering
    • LocationSearchResult
      Confluence144-174-04Nothing related

      144_174_04No results
      SEDA *144-174-04*No results
      V:\REG*144-174-04*???
      V:\REG\air_rfs\Projects *144-174-04*Nothing related, wrong number

      *144-174*Lots of results... lots of unrelated projects... closest numbers are located in Cryo_Sensor\RTM
      V:\CD\EIE\projects *144-174-04*Nothing related, wrong number
      V:\CD\David Brown\Fast PulseManually FOUND IT!!! ePIX HR Fast Pulse Schematic.pdf
      V:\CD*144-174-04*PcbDoc*
      V:\REG\air_rfs\Projects*144-174-04*PcbDoc*Nothing found
      V:\REG\air_rfs\Projects\Altium Libraries*144-174-04*PcbDoc*Nothing found
      Emailed David Brown-"not released" and PCBs are in a folder "PcbDoc"
      google drive???... too many files to search ...

      SLACers\Frisch\General\Fast PulseFOUND IT!!!
    • Main LocationLink
      V-DriveV:\CD\David Brown

      V:\REG\air_rfs\Projects\Cryo_Sensor\RTM\Rev_2\Brown, David G. - Cryostat_Board


      Google Drivehttps://drive.google.com/drive/folders/1BnV1H33AJJmZqOSrCbHZKSi8AZFmInnI



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