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High priority tasks and questions

The tasks and questions below should be looked at as soon as possible since they might be blocking

  • Can the DC/DC architecture be simplified? Some ICs not in stock, see DC/DC converters
    • Replace LMZ31530 (30A) with TPSM5D1806 in parallel mode (12A) since Vcc_int is estimated at 7A?
      • No, the 20A version should be available (LMZ31520)
    • Replace LT1764 with LT3083 for simpler paralleling circuitry (see power graph)?
  • Are the ASIC digital supply (G_DS_X) and I/O supply (G_IO_X) shared among all four ASICs?
  • Do we have the CML current consumption numbers?
    • Gang is saying around 20mA (15mA + 30% LVT) per ASIC TX Transceiver (for all frequencies). ASIC RX consumption is negligible 
    • Update power estimation table with these numbers
  • Request components for Altium library (see Altium Missing Components section)
    • Connectors have been requested on 2023-08-28
    • Other ICs
    • Transceiver
      • Compare with the layout done in PADS after to make sure it's correct orientation
  • Route +6V or +24V between analog and digital board?
    • If +6V: All first-stage converters (LT8648S) must be on one the board with the input TFM connector
    • +24V between boards
  • For the 0.6V sink:
  • On which board does the power connector (TFM) go and which type (TFM-112, TFM-115, etc)? (update Connectors section)
    • TFM-113-02-L-DH was used on the ePixHR250M_2x2_Camera
    • Analog board
  • Use FPGA transceivers for clocking the ASICs?
    • Yes 
    • One per ASIC?
      • Yes
      • I think one per ASIC is the best solution. Is there any reason why we should go for a clock splitter?
        • Probably no unless we run out of connector pins
  • Does the digital board need the analog ground (AGND)? (see 100kfps DAQ support system)
    • Will have it anyway since the TFM power connector is on the digital board
  • What's the expected operating temperature range?
    • -25C → +50C

ASIC level requirements summary

RequirementePixUHRSparkPix-SSparkPix-ED (question)
frame rate100kfps1Mfps1Mfps
Power supplies

2.5V Analog

1.3V (AS/DS/IO)

2.5V Analog

1.3V (AS/DS/IO)

0.6V (Current sink!)

1.3V (AS/DS/IO)
Power for each supplyePixUHR - 35 kHzSparkPix-S: supply/ground and power consumptiont.b.d.
Number of GT IOs per ASIC

8 (outputs)
1 clock in

8 (outputs)
1 clock in

t.b.d

(The current agreement is to have 8 outputs)

Expected I/O speed5.25 Gb/s5.25 Gb/s10 Gb/s (question)

Total data bandwidth

42 Gbit/s42 Gbit/s80 Gbit/s(question)




Target Cameras

There are three targeted cameras for this project:

  • 2x2 ePix/SparkPix
  • 1M ePix to later be used as building block for 16M camera
  • 2M SparkPix

Block diagrams

2x2 ePix/SparkPix

  • ePixHR/UHR 2x2 would be 140k pixels
  • SparkPix S would be 500k pixels

2x2-block-diagram

1M ePix

  • ePixHR/UHR in a 6x6 configuration would be 1.1M pixels
  • ePixHR/UHR in a 6x5 configuration would be 1M pixels

1M-block-diagram

2M SparkPix S

  • SparkPix S in a 4 x 4 configuration would be 2M pixels

2M-block-diagram

Parameter overview


2x2 ePix/SparkPix

1M ePix

2M SparkPix S

Parameter (estimated)

Small Camera 
ePixHR/UHR – 140k
2x2 ASIC

Small Camera 
SparkPix S – 500k
2x2 ASIC

Super tile
ePixHR/UHR – 1M
6x5 ASIC

Super tile
ePixHR/UHR – 1.1M
6x6 ASIC

Quad Camera 
SparkPix S – 2M
4x4 ASIC

Pixels

129,024 px
(168 *192*4)

540,672 px
(352*384*4)

967,680
(168 *192*30)

1,161,216 px
(168 *192*36)

2,162,688 px
(352*384*16)

Rate

35kHz / 100kHz

1MHz

35kHz / 100kHz

35kHz / 100kHz

1MHz

Focal Plane Area

4cm x 4cm

4cm x 4cm

12cm x 10cm

12cm x 12cm

8cm x 8cm

Front side footprint (window)

5cm x 5cm

5cm x 5cm

14cm x 12cm

14cm x 14cm

10cm x 10cm

Power (only ASIC)

0.016 kW/???

0.021kW0.130 kW/???0.144 kW/???0.084 kW

Weight

1.5kg

1.5kg

9Kg

10kg

6kg

Data volume 

56 Gbps/ 160 Gbps

160 Gbps

420 Gbps/ 1190 Gbps

504 Gbps/ 1440 Gbps

640 Gbps

From ASIC to FPGA

          168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame

@35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps

@100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps

From FPGA to PC

168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame

@32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps

@140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps

@1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps

@1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps

@4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps

@16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps

ASIC Power Requirements

ASIC Power Requirement

Analog Section

Digital Section

0.6V Sink

Analog TPS

ePixUHR 140k

2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

Voltage

1.3 V

1.3V

1.3V

1.3V

??? Maybe

0.6 V

2.5 V

2.5V

Required current

10A

(= 2.5 A* 4 ASIC)

13.4 A

(= 3.35A * 4 ASIC)

- With LVDS transceivers
1.2 A (= 4* 0.3 A)
-With CML transceivers

????

- With LVDS transceivers
2.0 A (= 4* 0.5 A)
-With CML transceivers

????

??? (If existing lower or equal than SparkPixS)

-8 A
(= -2A * 4 ASIC) 

0.4 A

(=0.1 * 4) 

0.4 A

(=0.1 * 4)  

System Requirement

+1.3 V @ +17.5 A

(+30% current safety margin)

+1.3 V @ +3 A

(+30% current safety margin)

[waiting for the CML number] 

+0.6 V @ -11 A

(+30% current safety margin) 

+2.5 V @ +0.5 A

(+30% current safety margin) 


FPGA Selection


ePixUHR 140k

2x2 Detector

Specs

ePixUHR 1.1M

6x6 Detector

Specs

ePixUHR 1M

6x5 Detector

Specs

SparkPix-S 500k

2x2 Detector

Specs

SparkPix-S 2M

4x4 Detector

Specs

KU15P (-A1156)

Kintex Ultrascale+

FPGA USED IN ePixHR250M

KU15P (-E1517)

Kintex Ultrascale+

KU15P (-A1760)

Kintex Ultrascale+

XCVU160 (-C2104)

Virtex Ultrascale

XCVU190 (-A2577)

Virtex Ultrascale

VU13P (-A2577)

Virtex Ultrascale+

General IO (HD, HP)






48 HD, 486 HP

96 HD, 416 HP

96 HD, 416 HP

52 HD, 364 HP

0 HD, 448 HP

0 HD, 448 HP

High Speed GTs (GTH/GTY)

- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbps/ 275Gbps

(1 Amphenol Transceiver)

Total:

48 High Speed GTs

- ASIC data:

288 = 8 lanes * 36 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12* 1.44 Tbps/ 275Gbps

(6 Amphenol Transceivers)

Total:

360 High Speed GTs

- ASIC data:

240 = 8 lanes * 30 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12 lanes * 1.19 Tbps/ 275Gbps

(6 Amphenol Transceivers)

Suggested 3 transceivers 1.4x compression in the detector

Total:

312 High Speed GTs

(If considering 5x2 Modules, 104 GTs each)


- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbps/ 275Gbps

(1 Amphenol Transceivers)

Total:

48 High Speed GTs

- ASIC data:

128 = 8 lanes * 16 ASIC

- Spare outputs :

0

- PGP communication:

24* = 12* 495 Gbps/ 275Gbps

(2 Amphenol Transceivers)

Total:

152 High Speed GTs

28
(20 GTH/8 GTY)

56

(32 GTH/24 GTY)

76

(44 GTH/32 GTY)

104

(52 GTH/52 GTY)

120

(60 GTH/60 GTY)

128

(0 GTH/128 GTY)

Total Block RAM






34.6 Mb

34.6 Mb

34.6 Mb

115.2 Mb

132.9 Mb

94.5 Mb

UltraRam, HBM






36 Mb, None

36 Mb, None

36 Mb, None

None, None

None, None

360 Mb, None

Transceiver Speed

 (GTH, GTY)

> 10 Gbps

> 10 Gbps

> 10 Gbps

> 10 Gbps

> 10 Gbps

GTH 16.3 Gb/s

GTY 16.3 Gb/s

Transceivers

GTH 16.3 Gb/s

GTY 32.75 Gb/s

Transceivers

GTH 16.3 Gb/s

GTY 32.75 Gb/s

Transceivers

GTH 16.3 Gb/s

GTY 30.5 Gb/s

Transceivers

GTH 16.3 Gb/s

GTY 30.5 Gb/s

Transceivers

GTY 32.75 Gb/s

Transceivers

Size

The PCB width is (preferably) 65 mm (2.56’’)





35 x 35 mm

40 x 40 mm

42.5 x 42.5 mm

47.5x47.5 mm

52.5 x 52.5 mm

52.5 x 52.5 mm

Cost






5-9 k$

 6-10k$

6-10 k$

40 k$

50-70 k$

60-110 k$

Comments






The number of GTs in this FPGA does not fit any of the cameras we are targetting

This is fine for the 2x2 Systems.

For the larger systems we need more than 3 FPGAs

This is fine for the 2x2 Systems.

This is fine for the SparkPix-S 4x4

This is fine for the 2x2 Systems.

This is fine for the 2x2 Systems (assuming we can fit the real estate).

This is fine for the 2x2 Systems.(assuming we can fit the real estate)

*Done considering 1% Occupancy instead of maxing out the transceivers

Summarizing Table



UHR 2x2SparkPix S 2x2SparkPix S 4x4UHR 5x6UHR 6x6

                              Requirements

Characteristics 

48 GTs48 GTs152 GTs312 GTs360 GTs

KU15P (-A1156) Kintex U+

28 GTs    / 352 mm2       / 10k$❌❌❌❌❌
KU15P (-E1517) Kintex U+56 GTs    / 402 mm2      / 10k$✅✅❌❌❌
KU15P (-A1760) Kintex U+76 GTs    / 42.52 mm2  / 10k$✅✅✅ (2 FPGA)❌❌
XCVU160 (-C2104) Virtex U104 GTs / 47.52 mm2  / 40k$✅✅✅ (2 FPGA)✅ (1 FPGA/module)❌
XCVU190 (-A2577) Virtex U120 GTs / 47.52 mm2  / 70k$✅✅✅(2 FPGA)✅ (1 FPGA/module)✅ (1 FPGA/module)
VU13P (-A2577) Virtex U+128 GTs / 52.52 mm2 / 110k$✅✅✅(2 FPGA)✅ (1 FPGA/module)✅ (1 FPGA/module)


       

ePixUHR 140k 2x2 Detector System


SparkPix S – 500k 2 x 2 ASIC Detector System

Power calculation SpreadSheet: UltraScalePlus_XPE_2023_140kpx.xlsm




System level

RequirementParametersNotes
Power supply24V consistent with the HR detector
Mechanical size

We would like to match the ePixHRM board dimensions to reuse cooling

Side entrance detector

  • Existing 75x175mmx58:
  • max envelope would be (100x175x75mm)

Digital board2.56x5.265"
Power and communication2.56x5.240"
Carrier

2.56x1.95"


  • Can we do it smaller?
  • What is the minimum amount of components that need to leave in this board?


System Power Consumption Breakdown

Domain

Portion

Final Voltages


LDOs




DC/DC


DC/DC












ANALOG











ASIC

G_AS_0

1.3V @4.4A

← +1.3V

LT1764 x2 (LDO)

Max 6A (= 3A x2)

← +1.8V (TBD)

TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

← +6 V




LT8648S x2

42V, 15A Synchronous Step-Down Silent Switcher 2

Max Current = 15*2 = 30A

(Around 93% efficiency for 24 to 6V at max load)

← +24 V



The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS.

The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W.

If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W.

The power drawn by the rest of analog voltages should be less than 2W.


So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W.

Considering the efficiency curves of the DC/DC converters:

34/85%/93% =

43W Total Analog Power

G_AS_1

1.3V @4.4A

← +1.3V

LT1764 x2 (LDO)

Max 6A (= 3A x2)

← +1.8V (TBD)

G_AS_2

1.3V @4.4A

← +1.3V

LT1764 x2 (LDO)

Max 6A (= 3A x2)

← +1.8V (TBD)

TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

← +6 V

G_AS_3

1.3V @4.4A

← +1.3V

LT1764 x2 (LDO)

Max 6A (= 3A x2)

← +1.8V (TBD)

G_VG_0

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A (= 1.5A x2)





← +2.5V






LT3086 (LDO)

Max 2.1A





← +3V


TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(>90%  efficiency for this loads)


← +6 V

G_VG_1

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A (= 1.5A x2)

G_VG_2

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A (= 1.5A x2)

← +6 V


G_VG_3

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A (= 1.5A x2)

G_AS_2V5

2.5V @ <0.5 A

← +2.5V












DIGITAL








ASIC

G_DS_0

1.3V @3A

← +1.3V

LT3086 x2 (LDO)

Max 4.2A (= 2.1A x2)

← +1.8V (TBD)

TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

← +6 V






LT8648S x2

42V, 15A Synchronous Step-Down Silent Switcher 2

Max Current = 15*2 = 30A

(Around 93% efficiency for 24 to 6V at max load)











← +24 V



For the digital consumption of the ASIC we do not have precise numbers regarding the new CML logic.

Let's assume a double consumption w.r.t the LVDS design.

1.3V*6A = 8W

LDO losses = 0.5*6A = 3W

11W / 85% / 93% = 14W(ASIC Digital)


Regarding the FPGA considering a worst case efficiency of the DC/DC:
17.1W /85%/93% = 21.5W (FPGA)


Worst case scenario, the remaining electronics will draw 1A, multiplied by 5.5V = 5.5W, which before the DCDC will become 5.5W /85 = 7W

42.5W Total Digital Power

G_DS_X

1.3V @???A (CML simulations?)

← +1.3V

LT3086 x2 (LDO)

Max 4.2A (= 2.1A x2)

← +1.8V (TBD)

G_IO_0

1.3V @???A(CML simulations?)

← +1.3V

LT3086 x2 (LDO)

Max 4.2A (= 2.1A x2)

← +1.8V (TBD)

TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

← +6 V



G_IO_X

1.3V @???A(CML simulations?)

← +1.3V

LT3086 x2 (LDO)

Max 4.2A (= 2.1A x2)

← +1.8V (TBD)






FPGA

VCCINT

0.85V @7.05 A

← +0.85V



LMZ31520 DC/DC Buck converter

20 A

(Around 90% efficiency)

← +6 V

VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX

1.8V @0.7A 

← +1.8V



TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

← +6 V


MGTAVCC +MGTYAVCC

0.9V @3.7A

← +0.9V



VCC_1.2V + MGTAVTT + MGTYAVTT 

1.2V @5.5A

← +1.2V



TPSM5D1806 (DC/DC)

PMIC

4.5-V to 15-V input

Dual 6A output

(Between 80 and 90 efficiency)






← +6 V




DAC/ADC/Misc

VDD_5V

+5V @ <1A

← 5V

LT3086 (LDO)

Max 2.1A




← +5.5V (TBD)



VDD_3V3

+3.3V @ <1A

← +3.3V

LT3086 (LDO)

Max 2.1A

VDD_1V8

+1.8V @ <1A

← +1.8V

LT3086 (LDO)

Max 2.1A










85.5W Total Power (Estimation without CML transceivers)

DC/DC converters

Component

Product number

Quantity

Input Voltage

Output Voltage

Max Current

Comment

DC/DC Step Down converterLT8648S43V to 42V0.6V to 42V15A
DC/DC PMICTPSM5D180674.5V to 15V0.5V to 5.5VDual 6A / Single 12A 
DC/DC Buck converterLMZ3152013V to 14.5V0.6V to 3.6V20A30A version (LMZ31530) not in stock
Low Noise LDOLT176482.7V to 20V1.21V to 20V3ALow Output Noise: 40µVRMS (10Hz to 100kHz)
LDO alternative to LT1764LT308381.2V to 23VAdjustable to 0V3ALow Output Noise: 40μVRMS (10Hz to 100kHz)
Low Noise LDOLT3086121.4V to 40V0.4V to 32V2.1ALow Output Noise: 40µVRMS (10Hz to 100kHz)
Negative Linear RegulatorLT30918–1.5V to –36V0V to –32V-1.5ALow Output Noise: 18µVRMS (10Hz to 100kHz)

Power Graph

power-graph

power-parallel-circuits

OLD Graph:

General I/O

ePixUHR Signals (single ASIC)

N# Pins


Power Digital Signals

N# Pins


Digital Core Signals

N# Pins


P&CB Signals

N# Pins

Waveform/ ASIC Ctrl

5


LDO enables

7


Env. Monitors

7


Misce

24

Clk

2 (0 if also clk_matrix is sent via GT)


DCDC Syncs

2


Bias DAC

4


Spare

6

Slow Ctrl (SACI/Sugoi)

4





HS DAC

4




Digital Monitor

2





HS ADC

6+24+8 =38










Miscellan

5










Jitter Cleaner

12




Total

13


Total

9


Total

70


Total

30


TOTAL = 13 * 4(n.Asics) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP

For single ended → check the electrical specification

Other components

Component

Product number

Board

Operation Voltage

Power consumption

N# I/O needed

Needs substitution?

Quad SPI Configuration Memory

MT25QU01GBBB8E12

Digital

1.8 V

Max 50 mA

4

No, we can use HR pins

JTAG


Digital

1.8/1.5/1.2 V


4

No, we can either use HR or go to 1.2V

Analog Monitor (SlowADC) ADC

ADS1217

Both (key at the analog board, optional at the digital board)

AVDD =3V, DVDD =1.8V

< 1 mA

7

Maybe. The datasheet guarantees operation for digital down to 2.7V,  in HR250 was put at 1.8. Check if it is fine!

Analog Monitor MUX (x5)

MAX4734

may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...)

AVDD =3V

< 1 uA

None

They are controlled by the ADC

Humidity sensor

HIH_5031_001

Analog board

3 V


None

No

Thermistor

NTC_NHQM103B375T10

Carrier

None

No

Oscillators

•371 MHz XLL726371.428571I

•156 MHz 536FB156M250DG

•48 MHz CX3225SB48000D0FPJC1

Digital

2.5 V



Both 1.8 V and 2.5V solutions can be found depending on the voltage we want to use

Clock Fanout

SI53340-B-GM

Digital

2.5 / 1.8V



Now is 2.5, probably can be switch to 1.8, but since its AC-coupled should not matter. Check if we can remove the 2.5 LDO

Clock Jitter cleaner

SI5345_64QFN

Digital

VDD = 3.3V, DVDD =1.8V


12 + n. clks


Programmable Oscillator

LMK61E2

Digital

3.3 V



Used?


High Speed ADC

AD9249

Analog

1.8 V

Max 58mW/channel:

58*12 = 700mW

38

No

ADC_MON_VCM Buffer

AD8607_MSO8

Analog

1.8V




Bias DAC (HV Ring)

MAX5443 (DAC) +

MAX14611 (Level Shifter) +

REF192GS  (Voltage reference)

Analog

3.0 V (VCCA)


4

Maybe? Will the sensors have an HV ring?

ASIC clk fanout

SI53340-B-GM

Analog


Probably not needed

HS DAC (Vcalib_p)

MAX5719A(DAC)+

MAX14611 (Level Shifter) +

OP213 (Buffer)

MAX6126A41+(Vref)

Analog

5V



Why was this chosen? Do we need the 5 V supply?

Level Shifter for Power controllers

MAX3378EETD (x2)

MAX3373E_SOT23_8 (x1)

to be defined

1.8V -> 3.3V




Serial number

DS2411R

Carrier, analog and digital boards

1.8V




Line Equalizer

(check the one used for cryo)

Analog




Nice to have

System level accounting

FunctionalityIO typeQuantityswitching specification
ASIC control (GR, ...)2.5V SE
Static
SUGOI


SACI


DATACLM?40 + spares?10Gbps
System IO


transceiver

25Gbps

supporting electronics




enablels for power


Slow ADC (current and voltage monitors, temperature sensors...)


HS ADC


serial number




HS DAC


Lower priority needs (R&D on system)


FPGA to FPGA interconnection

requires GT+specific connector

Transceiver

  • Ideal is to reuse the 300Gbps Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode power supply.

Board material 

  • Needs to be FR408HR or better

System level simulation 

  • GT to the ASICs
  • GT to the transceivers
  • Power drops

Connectors

FunctionalityObservations
Carrier to analog board
  • How are we going to prevent ePixHRM carriers to be connected in to the 100kfps digital board and vice-versa?
    • Options could be mechanical pins or change connector polarities
    • Or via serial ID (needs to have a database) via soft locks
  • Routes all power, data and control signals to/from the ASICs
Analog to digital board
  • Distributes the 24V from the power connector
  • Routes data and control signals between the ASIC on the carrier and the FPGA on the digital board
External power supply
  • Should be on the bottom board (digital) because a pigtail is connected to it that is attached to the outside shell
    • If if was on the top board (analog) there's a risk of damaging the ASICs and their wirebonds on the carrier
Optical transceiver
  • Same as for the power connector
  • Place close to FPGA due to 25 Gbit/s signals

connector-sideview

Grounding

  • Separate ground come into the system through the TFM power connector on the digital board
  • The HV supply ground and the Analog supply ground are connected to the same analog ground net
  • The digital supply is connected to the digital ground net
  • The analog and digital grounds are connected together on the digital board near the TFM power connector

grounding-diagram

Other notes

  • FPGA intercommunication
  • Co-design with the data reduction pipeline
  • DFX for streaming pre-processing and eventually microAI, reusable building blocks

Board design

Altium missing components

The components listed in the expansion box below are currently missing from the SLAC Altium library located on OneDrive (Altium_Yee_lib).

  • Components marked with (green star) are available from the Altium Manufacturer Part Search catalog with symbol and footprint
  • Components marked with (red star) have been created in a temporary library (schematic symbol only) which should be integrated into the OneDrive library at some point
  • Components marked with (blue star) have been requested
    • Components with strikethrough have been created after request

DC/DC

  • LT1764 (green star)
  • LT3091 (green star)
  • LT3086 (green star)
  • LT8648S (green star)
  • TPSM5D1806 (red star)
  • LMZ31520 (green star)

Connectors:

  • 30-pin
    • SEAF-30-06.5-S-06-2-A-K (red star)(blue star)
    • SEAM-30-11.0-S-06-2-A-K (red star)(blue star)
  • 50-pin
    • SEAF8-50-05.0-S-10-3 (red star)(blue star)
    • SEAM8-50-S05.0-S-10-3 (red star)(blue star)
  • TFM-115-02-L-DH (blue star)

FPGA:

  • (XCKU15P-2FFVA1156E used earlier in PC_261_101_25_C00)
  • (question) Speed-grade 1 or 2?
    • XCKU15P-1FFVA1760E
    • XCKU15P-2FFVA1760E (red star)

Thermistor, humidity:

  • NHQM103B375T10
  • HIH-5031-001 (green star)

AD/DA:

  • ADS1217 (green star)
  • MAX4734
  • AD8607 (green star)
  • MAX14611
  • REF192GS (green star)
  • MAX5719A
  • OP213 (green star)
  • MAX6126A41

ID:

  • DS2411R (green star)

Optical:

  • 10140369-101LF

Memory:

  • MT25QU01GBBB8E12 (red star)

Oscillator/clock:

  • XLL726371.428571I
  • 536FB156M250DG
  • CX3225SB48000D0FPJC1
  • SI53340-B-GM
  • SI5345_64QFN
  • LMK61E2

Level-shifters:

  • MAX3378EETD

Passives:

  • Capacitor 330uF/4V: AVX F950G337KBAAQ2

Digital board

The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.

digital-board-block-diagram

FPGA design resources

Analog board

The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.

analog-board-block-diagram

Carrier board

The carrier board contains the specific ASICs and any passive components that are needed.

carrier-board-block-diagram


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