Toroid Electronics Meeting Minutes

May 24, 2006

Concept Design Review

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Contents

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Attendees:

Agenda:

1. System Architecture
2. Board Architecture
3. Timing and Flowcharts
4. Project Timeline

Presentation Materials:

CDR Presentation, M. Cecere (PPT Format)
Toroid Charge Monitor Timeline, M. Cecere ( Project Format)

Minutes:

1. Presented MicroController based design
2. Discussed Analog Integrator Technique
   1. Dual Integrators twice as long to calibrate, change design for single integrator, staged sampling of output
   2. Bring in baseline and pulse signals for subtraction into PIC
   3. No need to bring Vcomp signal into IOC ADC
3. Network reprogrammability would be very useful for configuration management. (could be done with jumpers, prog header...)
   1. Program which toroids to compare.
   2. Program which toroid channels, comp channels are enabled
   3. Program MPS signalling thresholds Enable/Disable?
4. How to trigger IOC/MPS that data is ready?
   1. Need digital input to IOC to signal data ready on Vcharge analog lines
   2. Need/How to signal MPS that data has been updated?
5. need watchdog timer on EVR trigger arrival?
   1. Since Beam CAN be run in Single-Shot mode, determining a missing trigger is tricky
6. Faraday Cup accuracy ~10-15%
7. Question to Tim M., when is first articles rom ISA?
8. Need a Test Plan for this project

Action Items:

1. M. Cecere: Need ICD and Test Plan
2. M. Cecere: When is first article from ISA due?
3. M. Cecere: Check with Ron Akre on his boards' availability
4. M. Cecere: Determine handshaking scheme for IOC and MPS
5. M. Cecere: Redraw integrators with one integrator, 2 S/Hs
6. M. Cecere: Add Mechnical Box design to timeline
7. M. Cecere: Add fast digitizer coding, and coder, to timeline