Introductions
CHESS2 ASIC: Design Requirements
CHESS2 ASIC: Concept Presentation
CHESS2 ASIC: Pintout (v1.21)
CHESS2 ASIC: Datasheet (v1.16)
Useful Links
CERN Documentation
JIRA Bug Reporting
GIT Repo
Board Designs:
CHESS2 Carrier Board
CHESS2 Digital Daughter Board
HowTos
How to cable up the development board hardware
How to checkout the firmware/software from github
How to build the firmware
How to program the FPGA
How to build and run the software
Testing Notes
CHESS2 Testing notes
Contact
Dionisio Doering
ddoering@slac.stanford.edu