Overview

Acronyms

Linac Locking System-Level Description

A high-level description of the linac locking system is captured in the page linked below:

Linac Locking - A System Level Overview

IOC Description

IOC Deployment

In this section, we provide IOC deployment details such as the App hosting the PLL IOCs, as well as the IOC names and the assigned CPUs in both Dev and Production. 

IOC Repository

The IOC is housed in the masterSource App.  The intended released tag in Production is R2.2.3.

Deployment In Production

The configuration used in Production is seen below.

Deployment In Dev

The configuration used in Dev is seen below.  As of now, there is no designated test stand in Dev.

IOC Packages

List of required packages and associated versions.

IOC Modules

List of required modules and associated versions.

IOC Bootup

In this section, a detailed description of the IOC bootup process is laid out.

Generic variable definition

First, define the usual environment variables in the startup script.

Common setup

Load dbd and IOC health/monitoring records.  Also, set up autosave and load the LCLS access configuration file.  Finally, copy the archive file in $IOC_DATA to enable record archiving.

Yaml initialization

Load the YAML hierarchy and register configuration.

Autosave initialization

Tell the IOC where to find the list of record names that will be autosaved.

Besides the auto-generated record names for autosave, copy the manually generated list of records to be autosaved.

Database loading

Load the PLL EPICS records.

Asyn driver configuration

Create the ycpswAsynDriver with a dictionary option, i.e. use a limited number of interfaces to the FPGA registers, and load the YAML tree hierarchy.

Archiver list

A complete list of the records to archive is provided below.

IOC initialization

Initialize the IOC and logging capability.

Autosave start

Start the autosave process. 

Algorithms

EPICS Records

A complete list of the PLL IOC Process Variables (PVs) can be found in the page linked below, Look for Section PLL Loop for  L0-L1 PRL (L0-L1 VCO Control).

PV name for LCLS2 Master Source

Displays

Displays in both Dev and Production exist for the control of the PLLs.

Dev

To access and launch the display in Dev, follow the steps outlined below. 

For the 11.5MHz PLL GUI:

(base) skoufis@aird-b50-srv01  (master) $ cd $EPICS_IOCS/sioc-b084-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/ 
(base) skoufis@aird-b50-srv01  (master) $ ./prl115_b084_screen

For the 476MHz PLL GUI:

(base) skoufis@aird-b50-srv01  (master) $ cd $EPICS_IOCS/sioc-b084-ms08/iocSpecificRelease/masterSourceApp/srcDisplay/ 
(base) skoufis@aird-b50-srv01  (master) $ ./prl476_b084_screen

Production

To access and launch the display in Production, follow the steps outlined below. 

For the 11.5MHz PLL GUI:

[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl115_screen

For the 476MHz PLL GUI:

[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms08/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl476_screen

Deliverables

The released software and firmware will be made available for access.  See the remaining content of this section for the specific repositories and tags.

Software Release

See software release details below.

Firmware Release

See firmware release details below.

References