The ePixHR5kHz is one of the first in-house LCLS-II detectors in development and is targeted at being a replacement for the ePix10ka, with the capability to run data 5kHz frame rate. The prototype has been built within the mechanical envelope of a front-facing small ePix10k as can be seen in Figure 1.
Figure 1. Image of the ePixHR prototype camera.
A single ASIC (v2) has been attached to the carrier board and a small sensor (48x48 pixels). The sensor has a standard entrance window, i.e., not the thin entrance window intended for the final detectors. The requirements that the detector was designed for and the measured results stated by TID for (Matrix+ADC) can be seen below:
Table 1. Design requirements and measured performance of key characteristics.
Requirements | Results | |
Mode of Operation | Integrating with: •auto-ranging high-low •auto-ranging medium-low •fixed high gain •fixed medium gain •fixed low gain | Integrating with: •auto-ranging high-low •auto-ranging medium-low •fixed high gain •fixed medium gain •fixed low gain |
Pixel size | 100x100 µm2 | 100x100 µm2 |
Range | Auto-ranging: >40000 keV (transitions 400keV/1200keV selectable) Fixed high gain: >400 keV Fixed medium gain >1200keV Fixed low gain: >40000 keV | Auto-ranging: 64000 keV (transitions 400keV/1200keV selectable and tunable) Fixed high gain: 880 keV Fixed medium gain 2640keV Fixed low gain: 64,000 keV |
Noise r.m.s. | < ~400eV (~110e-rms) | ~ 270eV* (~75e-rms)* |
As stated in the table, the detector has a 100um pixel pitch and can be configured in 5 different gain modes; 3 fixed gain modes and 2 auto-ranging gain modes. As with the other members of the ePix family of detectors, the analogue chain consists of a CSA with a switched reset scheme, a 1st order low pass filter, and a correlated double sampler. The CSA has been designed with the option to vary the feedback capacitance of the CSA, effectively changing the gain of the system.
Figure 3. Analogue channel layout for the ePixHR5kHz pixel.
The pixel array size for the detector is 192x144. Figure 2 show a depiction of the ASIC layout with core blocks highlighted.
Figure 2. Image of the ASIC functional blocks.
In order to facilitate the high framerate the number of ADC boards at the edge of the ASIC was increased, giving raise to the balcony seen in both Figures 1 and 2. The structure of the analog channel for the ePixHR5kHz, with the additional optimizations done compared to the ePix10ka channel, highlighted, can be seen in Figure 3.