Note: we never touch this. ADC pipeline delay used to mean something but doesn't since the introduction of Maciej's auto-ADC-alignment procedure.
/reg/g/pcds/dist/pds/current/build/pdsapp/bin/x86_64-rhel7-opt/configdb_readxtc /reg/d/psdm/mfx/mfxc00120/xtc/ -e on run 181.
EVR timing?
Special information for ePix100 at TMO setup in psana2?