This is a short specification to help the firmware developer to integrate the DaqMux in his firmware.
Overview
The DaqMux was originally developed as an oscilloscope to transmit streams from the FPGA to software for debugging purposes. Then it started being used as a data streamer by the application to software, and it's configurations were exported to EPICS/software.
Feature summary
The DaqMux can perform the following functionalities
- Multiplex up to 4 streams (lanes) and send forward (to software)
- Stream packets can be acquired continuously every time a trigger arrives in continuous mode, or only once upon trigger with or without header (meta data) in trigger mode, or many times with or without header (meta data) in trigger mode when auto re-arm is enabled
- Possibility of cascading trigger of DaqMux blocks in case streams from several DaqMuxes acquired at the same instant is required
- Pause streaming by not overwriting buffers (freeze functionality), therefore nothing is forwarded to software
- Down sampling and averaging
Definitions
- Stream : a group of bytes transmitted in sequence.
- Lane : a physical bus at which the stream crosses
- Packet : User abstraction. Bunches of bytes that the user wants forward to software from each lane every time there is a trigger
- AXI transaction : Hardware abstraction. Packets are broken into a 1 or more AXI transactions
Applications
Figure 1 shows the DaqMux instantiated in the Common platform firmware in the application side.
Figure 1: Common platform firmware top-level
Generics & IO description
Table 1: DaqMux generics list and description
| Generic name | default value | Description |
|---|---|---|
| TPD_G | 1 | Simulation variable; register clock to output delay in nanoseconds |
| DECIMATOR_EN_G | True | Decimator enable |
| WAVEFORM_TDATA_BYTES_G | 4 | Output lane width in bytes |
| FRAME_BWIDTH_G | 10 | Power of two, which defines AXI stream transaction size in words (4 bytes)(i.e. when FRAME_BWIDTH_G = 12 → 210 x 4 = 4096 bytes) |
| BAY_INDEX_G | - | Index of the DaqMux |
| N_DATA_IN_G | 16 | Number of input data lanes |
| N_DATA_OUT_G | 4 | Number of output data lanes |
| Name | Direction | Clock domain | Width | Description |
|---|---|---|---|---|
| axiClk | Input | - | ||
| axiRst | Input | axiClk | ||
| devClk_i | Input | |||
| devRst_i | Input | |||
| trigHw_i | Input | |||
| trigCasc_i | Input | |||
| trigCasc_o | Output | |||
| armCasc_i | Input | |||
| armCasc_o | Output | |||
| freezeHw_i | Input | |||
| timeStamp_i | Input | |||
| bsa_i | Input | |||
| dmod_i | Input | |||
| axilReadMaster | Input | |||
| axilReadSlave | Output | |||
| axilWriteMaster | Input | |||
| axilWriteSlave | Output | |||
| sampleDataArr_i | Input | |||
| sampleValidVec_i | Input | |||
| linkReadyVec_i | Input | |||
| wfClk_i | Input | |||
| wfRst_i | Input | |||
| rxAxisMasterArr_o | Output | |||
| rxAxisSlaveArr_i | Input | devClk_i | ||
| rxAxisCtrlArr_i | Input | devClk_i |
Functional description & block diagrams
Register address mappings and description
Clocking/performance requirements
Connectivity
Overview
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