three pieces:
- eval board with camera (only in medium)
- kcu1500
- software (uses rogue)

python scripts/gui.py

~rherbst/projects/lcls2/lcls2-pcie-apps/software/TimeTool

gui.py has clinktest is everything on front-end board
clinktop is camera section of front-end board
global and two channels of configuration

linkreset: resets receiving logic from camera
A, B, C are the 3 data interfaces
shiftcount/delay have to do with sampling the 533MHz clock

channela:
linkmode: using medium 8bit
framemode: our camera only gives a line valid (indication that there is valid data)
tapcount: our camera sends 4 bytes where it could send 6
dataen: enables the data block (leave false until able to receive data)

swcontrolvalue/swcontrolen: bits for hardware vs software trigger (0/0 internal trigger)

running: status bit (am I getting frames from camera)
dropcount: 3 channels misaligned (errors)

front-end board gui:
Commands/Command:
- sendescape: puts it into the mode where you can send it strings
(alternative: cameralink mode)
- sendstring: sequence of characters to configure
- sendGCP: Get Configuration Parameters

VC's: front-end, camera serial, camera data

on the "variable page":
-

roque command is a "subclass" of a variable: does a sequence of
actions

variables/HW is interacting with the kcu1500
- linkready under "link0/monitor"

timetooldev/timetooldev/timetool: addvalue (adds a value to every byte)

timetoolrx: is a software element

timetooldev class:
- hard reset, soft reset, count reset are user-definable
- currently pgp classes reset their counters

- load/save settings saves all read/write variables
- can subclass "data file" that will store data

slaclab/lcls2-pcie-apps:
-firware/targets/TimeToolKcu1500
- store toplevel code in TimeToolKcu1500.vhd
- contains pgp/pcie stuff

kcu1500 core contains dma/pcie
hardware block contains pgp2b core and timing-receiver core (in "common" repo)

kcu1500 -> axi-lite-but + 8 axi-stream data busses

stealing one virtual channel from the one of the 8 axi-streams, called
a "stream tap".

axi streams have 256 "destinations" (like VC's)

can add a "crossbar" which splits out the registers/data

firmware/applications/TimeTool/python/TimeTool.py
/hdl/TimeToolCore.vhd

edit the above, and built in "targets"
this is the code to add the "1"

two-process vhdl

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