NRC Development

This page captures various information about the development of the NRC.

The CERN website, NRC, contains the plan and additional information.

Firmware

Module	Register description	Function
Core		Version information and clock selection
BUSY	AtlasCscBusyReg	DTM TTC and BUSY forwarding
TTCrx	AtlasTtcRxReg	DPM TTCrx block
TTCem	AtlasTtcTxEmuReg	DTM TTC emulator
SCA	AsmPackCtrlReg	Switched Capacitor Array Controller block
FEX	AtlasAsmPackFexReg	Feature EXtraction block
FEX-lite	AtlasAsmPackFexLiteReg	Simple FIFO interface to FEX input header data
ROL	TBD	Read-Out Link block

Directory	Description
`common`	Common helper code
`hal`	Hardware Abstraction Layer
`rci`	Remote Communications Interface
`fee`	Front-End Electronics interface for the FEX RCEs
`rol`	Read-Out Link interface for the Formatter RCEs
`supervisor`	The bridge code for interfacing between the Control side and the Real-Time sides
`app`	NRC Application launching code
`CSCModules`	The Control Processor code, comprising of both stand-alone code and the TDAQ interface

SCons: man
SConstruct file describe how to build the project.
SConscript files describe how to build the packages of the project.
Site-specific: file:///afs/slac.stanford.edu/g/cci/repositories/nrc/scons
- JJ's ImportProject description

l1aDrain (RTEMS only): Reads the TTCrx FIFO as fast as possible.
fexDrain (RTEMS only): Reads the TTCrx and FEX-lite FIFOs as fast as possible.