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Building firmware

ISE

Vivado

  • XAPP890 - Zynq All Programmable SoC Sobel Filter Implementation Using the Vivado HLS Tool

Configuration

  • ug470 - 7 Series FPGAs Configuration User Guide

Partitions and partial reconfiguration

  • Partial Reconfiguration in the ISE Design Suite
  • Zynq 7000 Partial Reconfiguration Reference Design
  • ug702 - Partial Reconfiguration User Guide
    • NB, this says "Partial Reconfiguration is not currently supported in the Vivado Design Suite." 
    • This comment is apparently out of date; xapp1159 implies that Vivado can be used.
  • ug744 - Partial Reconfiguration of a Processor Peripheral Tutorial
  • xapp1159 - Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices
  • xapp918 - Incremental Design Reuse with Partitions
  • xapp290 - Differencing Method for Partial Reconfiguration
    • This seems to be an alternate method to using reconfigurable regions, described in the other documents.
    • It is not advised to use this method if routing changes are desired.
    • This method is good for changing I/O standards, block RAM contents, and LUT programming.   
  • tool/fpga contains code for (re)loading the FPGA fabric
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