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  • Execution after reset starts at 0xfffffffc
    • A branch instruction to some boot code is loaded here
      • The Xilinx example branches to in block RAM (bram) at 0xffffff00
    • Potentially a sc (system call) instruction could be loaded here? Any advantage to this?
      • Probably not as the corresponding ivor register (PPC 440) is not loaded yet
  • In our case, the boot code starts at startup
    • Other names are start, download_entry and __rtems_entry_point
  • Boot code vaguely follows the "Initialization Software Requirements" outlined in the PowerPPC 440x6 Embedded Processor Core User's Manual v7.1 from IBM
    • Why only "vaguely"?
  • Clear MSR
  • Disable debug events
  • Configure instruction and data cache registers
  • Set up decrementer and timer registers
  • Clear exception registers ECR and XER
  • Invalidate instruction and data caches
  • Clear the CPU reservation bit
  • Set up CCR0, CCR1, MMUCR, CRF (question) and CTR
  • Set up TLB pages
  • Set up debug events
  • Set up EABI and SYSV environment
  • Clear out BSS section
  • Load vector offset register
  • Set up TOC (? r2 overwritten?)
  • Set up initial stack
  • Set up argument registers r3, r4 and r5
  • Branch to boot_card
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