LZ Test Stand Electronics Phase 2

• Previous preamp and digitizer design:
  • PC_264_800_03_C00
  • PC_264_800_02_C00
• Gunther's presentation
• Larry's Rough Draft

Fast ADC for high gain (2x) channels:

• ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS
  • http://www.ti.com/lit/ds/symlink/ads54j60.pdf
  • 1.35W / channel = 10.8W for 8 high speed channels
  • Cost each = $850. Total cost for 8 channels = $3400.
  • Need 2 JESD channels per ADC, 16 total
  • Block diagram
    
    
• ADS54J54IRGCT Quad Channel, 500 MHz sampling, 14-bit
  • http://www.ti.com/lit/ds/symlink/ads54j54.pdf
  • 0.875W / channel = 7W for 8 high speed channels
  • Cost each =  $795. Total cost for 8 channels = $1590.
  • Need 2 JESD channels per ADC, 16 total
  • Block diagram

Slow ADC for low gain (0.5x) channels:

• ADC3444 Quad-Channel, 14-Bit, 125-MSPS
  • http://www.ti.com/lit/gpn/ADC3444
  • 0.098W / channel = ~1W for 8 channels
  • Cost each = $160. Total cost for 8 channels =  $320.
  • Uses LVDS IOS. 

For the FPGA we can use a XCKU040 part for about $800

Parameters from meeting of 27 October:

Bandwidth Lower Limit = 10 kHz

Bandwidth Upper Limit = 500 MHz

Sampling Rate = 1 GHz

1 p.e. distribution probable lower limit ~ 1 mV

maximum signal = 1e4 p.e.