Title: (Deprecated, but good links) Building/Running TimeTool Software and Firmware  
Author: Christopher O'Grady Jan 26, 2018
Last Changed by: Christopher O'Grady Apr 30, 2020
Tiny Link: (useful for email) https://confluence.slac.stanford.edu/x/egrMDQ
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Incoming Links
LCLS Data Analysis - Internal (1)
    Page: how to use pyrogue from python shell
Hierarchy
Parent Page
    Page: Timetool for LCLS-II
Children (16)
    Page: (Deprecated) remote reboot FPGA machine
    Page: AMBA® 4 AXI4-Stream Protocol Version: 1.0 Specification
    Page: AMBA® AXI™ and ACE™ Protocol Specification
    Page: FIR Compiler v7.2
    Page: Good examples of modules that touch the data frames
    Page: High Level Block Diagram
    Page: how to use pyrogue from python shell
    Page: ILA core generation visual step through
    Page: instructions for lcls2-pgp-fw-lib-update
    Page: Instructions for running vivado simulation
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Recent Changes
Time Editor  
Apr 30, 2020 15:44 Christopher O'Grady View Changes
Feb 20, 2020 11:33 Christopher O'Grady View Changes
Feb 13, 2020 15:26 Christopher O'Grady View Changes
Dec 06, 2019 13:52 Christopher O'Grady View Changes
May 14, 2019 14:07 Christopher O'Grady  
Outgoing Links
External Links (30)
    https://github.com/slaclab/rogue/blob/master/README.md
    https://github.com/slaclab/lcls2-pcie-apps
    https://www.xilinx.com/support/answers/59128.html
    https://docs.google.com/presentation/d/1QaUZmsM9fOA6M3zlxPC…
    https://slaclab.github.io/surf-doc/surf_1_documentation/htm…
    https://github.com/slaclab/lcls2-pcie-apps/blob/master/soft…
    https://github.com/slaclab/surf
    https://help.github.com/articles/adding-a-new-ssh-key-to-yo…
    https://www.xilinx.com/support/documentation/user_guides/ug…
    https://docs.google.com/presentation/d/1VVfkIWN9M_czZiaXhK4…
    https://github.com/slaclab/lcls-timing-core/blob/4de46d35c3…
    https://github.com/slaclab/lcls2-pcie-apps.git
    https://github.com/slaclab/rogue/blob/master/Readme_python3…
    https://github.com/slaclab/lcls-timing-core/blob/release-lc…
    https://www.xilinx.com/support/answers/59751.html
    https://slaclab.github.io/rogue/
    https://github.com/slaclab/cameralink-gateway
    https://www.xilinx.com/support/documentation/sw_manuals/xil…
    https://github.com/slaclab/lcls2-timetool/blob/master/softw…
    https://www.xilinx.com/support/documentation/sw_manuals/xil…
    slac.stanford.edu/g/reseng/xilinx/vivado_2017.4/Vivado/2017…
    https://github.com/slaclab/lcls-timing-core/blob/589c8bc10d…
    https://github.com/slaclab/l2si/blob/master/firmware/common…
    https://docs.google.com/presentation/d/1RMB0pxKQXMMOqtIbARz…
    https://github.com/slaclab/rogue/blob/master/Readme_build.t…
    https://github.com/slaclab/lcls-timing-core/blob/release-lc…
    https://forums.xilinx.com/t5/Synthesis/How-to-display-post-…
    https://docs.google.com/presentation/d/10eIsAbLmslcNk94yV-F…
    https://github.com/slaclab/lcls-timing-core/blob/release-lc…
    https://github.com/slaclab/lcls2-pcie-apps/blob/master/soft…
LCLS Data Analysis - Internal (2)     Page: how to use pyrogue from python shell
    Page: ILA core generation visual step through
TID Advanced Instrumentation for Research Division (1)     Page: AxiStream Batcher Protocol Version 1