@christopher o'grady/@Sioan Zohar: Here's the new PCIe image from my development branch for you guys to test:
https://github.com/slaclab/lcls2-pcie-apps/commit/6a8cea510566860124262be8cab2a84c2bb518ed

Here's the instructions for updating the PCIe card:
https://github.com/slaclab/lcls2-pcie-apps/tree/master/software/TimeTool#how-to-reprogram-the-pcie-firmware-via-rogue-software

Here's the instructions for updating the FEB board:
https://github.com/slaclab/lcls2-pcie-apps/tree/master/software/TimeTool#how-to-reprogram-the-feb-firmware-via-rogue-software

Here's the configurations that I used in my testing (standalone LCLS-I timing with 120Hz fiber triggering):
https://github.com/slaclab/lcls2-pcie-apps/blob/master/software/TimeTool/config/defaults.yml

Here are the instructions for running the SW/FW co-simulation using Rogue + VCS:
https://github.com/slaclab/lcls2-pcie-apps/tree/master/software/TimeTool#how-to-run-the-rogue-pyqt-gui-with-vcs-firmware-simulator

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re-syncing

I would avoid the hardReset command. If you do a hardReset or lose link, I would do the following:
1) set EventBuilder.Blowoff to True
2) Turn off the fiber triggers (Hardware.Timing.Triggering.LocalTrig[0]EnableTrig = False)
3) Set EventBuilder.Blowoff to False
4) Turn back on the triggering (Hardware.Timing.Triggering.LocalTrig[0]EnableTrig = True)

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