IOC names and PV prefixes

IOC name	CPU name	PV prefix (<device>:<area>:<position>)	Description	Location	Associated network nodes	Notes
sioc-sys0-ms01	cpu-sys0-sp01	FREQ:SYS0:00 SIM01 (SIM YCPSW PVs) PRL:SYS0:1:MO	PVs for Master Oscillator in master source rack MO freq locker SIM modules for freq. locker (SIM01) Agilent freq. counter (FREQ:SYS0:00) RF-locking Matlab script (Charlie Xu, "LCLS2_MO_Frequency_locker_PID") (PRL:SYS0:1:MO)	L2KG02-25		L2KG02-25	Freq. counter: freq-sys0-ms01 Freq. counter: freq-sys0-ms01 FPGA: 192.168.1.16
sioc-sys0-ms02	cpu-sys0-sp01	PRL:SYS0:02 (SIM high-level PVs) SIM02 (SIM YCPSW PVs) PRL:SYS0:02:L0 (Beckhoff PA PVs) PRL:SYS0:02:01 (Beckhoff rack PVs) BKHF:SYS0:MS02 (Beckhoff low-level PVs)	PVs for SIM modules in master source rack and Beckhoffs in laser rack SIM for L0-L1 PLL master (SIM02) Beckhoff for: L0-L1 VCO (slave) PA L2CID-04 rack temp & water flow	L2KG02-24 (SIM) L2CID-04 (Beckhoff)	Beckhoff: apc-sys0-ms02 FPGA: 192.168.1.20
sioc-sys0-ms03	cpu-sys0-sp01	PRL:SYS0:03 (SIM Pvs) SIM03 (SIM YCPSW PVs) PRL:SYS0:03:L2 (Beckhoff L2 VCO PVs) PRL:SYS0:03:L3 (Beckhoff L3 PVs) PRL:SYS0:03:LO (Beckhoff LO PVs) PRL:SYS0:03:01 (Beckhoff rack PVs) BKHF:SYS0:MS03 (Beckhoff low-level PVs)	PVs for SIM modules in master source rack and Beckhoffs in LLRF rack SIM for L2 PLL master (SIM03) Beckhoff for: L2 VCO (slave) PA L3 PA L3 LO PA L2KG02-20 rack temp & water flow	L2KG02-24 (SIM) L2KG04-20 (Beckhoff)	Beckhoff: apc-sys0-ms03 FPGA: 192.168.1.28
sioc-sys0-ms04	cpu-sys0-sp01	PRL:SYS0:04:L0 (Beckhoff L0-L1 PVs) PRL:SYS0:04:L2 (Beckhoff L2 PVs) PRL:SYS0:04:LO (Beckhoff LO PVs) PRL:SYS0:04:01 (Beckhoff L2KG02-24 rack PVs) PRL:SYS0:04:02 (Beckhoff L2KG02-25 rack PVs) BKHF:SYS0:MS04 (Beckhoff low-level PVs)	Pvs for Beckhoffs in master source rack* L0-L1 return PA L2 return PA L0-L1 & L2 LO PA L2KG02-24 rack temp & water flow L2KG02-25 rack temp & water flow * Separated from sioc-sys0-ms01 at HW engineer's request	L2KG02-24 L2KG02-25	Beckhoff: apc-sys0-ms04
sioc-sys0-ms05	cpu-sys0-sp01	PRL:SYS0:05 (SIM PVs) SIM05 (SIM YCPSW PVs)	PVs for SIM modules in laser rack SIM for L0-L1 PLL slave (SIM05)	L2CID-04	FPGA: 192.168.1.19
sioc-sys0-ms06	cpu-sys0-sp01	PRL:SYS0:06 (SIM PVs) SIM06 (SIM YCPSW PVs)	PVs for SIM modules in LLRF rack SIM for L2 PLL slave (SIM06)	L2KG04-20	FPGA: 192.168.1.24

Frequency Locker PVs

MO DAC Control PVs

<prefix> = FREQ:SYS0:00

<SIM_prefix> = SIM<NN>

NN = two-digit IOC number

SIM FPGA MAC-IP mapping

IOC	Desc	Location	SN	MAC	IP
sioc-sys0-ms01	Freq locker	L2KG02-25	16	08:00:56:00:46:86	192.168.1.16
sioc-sys0-ms02	L0-L1 PLL master	L2KG02-24	20	08:00:56:00:46:16	192.168.1.20
sioc-sys0-ms03	L2 PLL master	L2KG02-24	28	08:00:56:00:49:55	192.168.1.28
sioc-sys0-ms05	L0-L1 VCO (slave)	L2CID-04	19	08:00:56:00:46:15	192.168.1.19
sioc-sys0-ms06	L2 VCO (slave)	L2KG04-20	24	08:00:56:00:46:FC	192.168.1.24

...

PV names

Frequency Locker PVs

MO DAC Control PVs

<prefix> = FREQ:SYS0:00

<SIM_prefix> = SIM<NN>

NN = two-digit IOC number

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

volt = Fixed1817toFloat(u) * 5.;

PV name	Description	Remarks (register name)	YCPSW name	Alarm Limits
<prefix>:SIMVER	Firmware version number for MoFreqLocker Module	Version	<SIM_prefix>:M:MFL:Version:Rd
<prefix>:MODAC_RBV	Readback value for
PV name	Description for PV	Remarks (register name)	YCPSW name	Calculaton Formula
<prefix>:SIMVER	Firmware version number for MoFreqLocker Module	Version	<SIM_prefix>:M:MFL:Version:Rd
<prefix>:MODAC_RBV	Readback value for DAC_OUTPUT3_REMOTE register	DAC_OUTPUT3_REMOTE	<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:Rd	Value inside FPGA is a 18bit signed 2'comp value. MATLAB expect value to be a non-offset signed binary range from +/-(2^(18-1)) This value should not be displayed Instead, there should be a separate PV that converts this value, and map to +/-5V. Because this is the real value that makes the most sense to any operators beside the developer
<prefix>:MODACVOLT	DAC readout in Volt	Soft PV [-5...+5V]	<prefix>:MODAC	Set value to DAC_OUTPUT3_REMOTE register	DAC_OUTPUT3_REMOTE	<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:St	Value inside FPGA is a 18bit signed 2'comp value. MATLAB expect value to be a non-offset signed binary range from +/-(2^(18-1)) This value should not be displayed Because there is an MATLAB high level app running. Only the readback value should be display

MO RF-locking Matlab script PVs

:Rd

<prefix>:MODACVOLT

DAC readout in Volt

Soft PV [-5...+5V]

LOLO: 1.0

LOW: 1.2

HIGH: 1.8

HIHI: 2.0

<prefix>:MODAC

Set value to DAC_OUTPUT3_REMOTE register

DAC_OUTPUT3_REMOTE

<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:St

MO RF-locking Matlab script PVs

<prefix> = PRL:SYS0:1:<prefix> = PRL:SYS0:1:MO

Script name: LCLS2_MO_Frequency_locker_PID

PV name	Description	RemarksUnits	Alarm Limits
<prefix>:VTUNE_VOLT	V tune voltage	ao, V
<prefix>:FREQ	Frequency readback	ao, Hz
<prefix>:LOCK_ENABLE	Lock enable/disable	bo, 0=Enable,1=Disable	ZSV: NO_ALARM OSV: MAJOR
<prefix>:FREQ_SETPT	Frequency setpoint	ao, Hz	TODO LOLO: LOW: HIGH: HIHI:
<prefix>:FREQ_ERR	Frequency error	ao, Hz	LOLO: -0.15 LOW: -0.07 HIGH: 0.07 HIHI: 0.15
<prefix>:WDOG_CNT	Watchdog count	longout

Frequency Counter PVs

Note: all <attribute> names are from the frequency counter Agilent53220A driver module.

...

PV name	Description for PV	Remarks
<prefix>:FREQ_RBCK_PROC_	Internal PV for Agilent53220A package When the frequency read back value is valid, it pushes the value to the rea back PV	No use for user level
<prefix>:SET_TRIG_LEVEL	Set trigger level in voltage
<prefix>:SET_TRIG_PERCENT	Set trigger level (relative, in %)
<prefix>:asyn
<prefix>:UPDATE	Internal PV for Agilent53220A package	No use for user level
<prefix>:GET_IMPEDANCE	Get input impedance	1M Ohm or 50 Ohm
<prefix>:GET_COUPLING	Get input coupling	AC or DC
<prefix>:GET_NOISE_REJ	Get noise rejection	ON or OFF
<prefix>:RESET	Reset and update all status PVs
<prefix>:SET_IMPEDANCE	Set input impedance	1M Ohm or 50 Ohm
<prefix>:SET_COUPLING	Set input coupling	AC or DC
<prefix>:SET_NOISE_REJ	Set noise rejection	ON or OFF
<prefix>:GET_AUTO_LEVEL	Get input auto level status	OFF/ON/ONCE
<prefix>:IDENTITY	Get IDN
<prefix>:FREQ_RBCK_RAW	Frequency Readback value (raw value)
<prefix>:FREQ_RBCK	Frequency Readback value (in Hz)
<prefix>:GET_TRIG_LEVEL	Get trigger level
<prefix>:GET_TRIG_PERCENT	Get trigger level (relative)
<prefix>:SET_AUTO_LEVEL	Set input auto level	OFF/ON/ONCE
<prefix>:GET_ROSC_SOUR	source selection for reference oscillator (readback)	INT/EXT
<prefix>:SET_ROSC_SOUR	source selection for reference oscillator (set value)	INT/EXT
<prefix>:GET_ROSC_EXTFREQ	Frequency readback for extern reference oscillator	1MHz/5MHz/10MHz
<prefix>:SET_ROSC_EXTFREQ	Frequency Set Value for external reference oscillator	1MHz/5MHz/10MHz
<prefix>:GET_DISPDIG_AUTO	display digit auto option (readback)	OFF/ON
<prefix>:SET_DISPDIG_AUTO	display digit auto option (set value)	OFF/ON
<prefix>:GET_DISPDIG	number of digit for display (readback)
<prefix>:SET_DISPDIG	number of digit for display (set value)

SIM PLL (master) PVs

...

Calculation Formula

18_17bit signed 2'comp value, so decimal value ranges +/-1. Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

Phase Shift:PhaseShift:St

18_17bit signed 2'comp value, so decimal value ranges +/-1. Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

0: for normal operation

1: ResetloopfilterintegralLOOPFILTTER_RESET value for loop filter resetLoop ResetLoopReset

0: for normal operation

1: Resetloopfilterintegral

18_17bit signed 2'comp value, so decimal value ranges +/-1. Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

18_17bit signed 2'comp value, so decimal value ranges +/-1. Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

<SIM_prefix>:M:PRLMST:Input_MUX:Rd

18_17 signed 2'comp registers, max value is between almost -1 and 1. The value is normalized to 1 from the 1.8V amplitude ADC. This is amplitude, not peak to peak value

1 = 1.8V

-1 = -1.8V

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

volt = Fixed1817toFloat(u) * 1.8;

18_17 signed 2'comp registers, max value is between almost -1 and 1. The value is normalized to 1 from the 1.8V amplitude ADC. This is amplitude, not peak to peak value

1 = 1.8V

-1 = -1.8V

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

volt = Fixed1817toFloat(u) * 1.8;

0 - loop enable

1 - loop disable:St

0 - loop enable

1 - loop disable

0 - normal operation

1 - state machine reset

0 - normal operation

1 - state machine reset

PV name	Description for PV	Remarks (register name)	YCPSW name	Alarm Limits
<prefix>:SIMVER	Firmware version number for Lcls2 PRL Master SIM	Version	<SIM_prefix>:M:PRLMST:Version:Rd
<prefix>:PHASESHIFT_RBV	readback value for additional phase shift	PhaseShift	<SIM_prefix>:M:PRLMST:PhaseShift:Rd
<prefix>:PHASESHIFT	set value for additional phase shift	Phase Shift	<SIM_prefix>:M:PRLMST:PhaseShift:St
<prefix>:LOOPFILTER_RESET_RBV	readback value for loop filter reset	LoopReset	<SIM_prefix>:M:PRLMST:LoopReset:Rd
<prefix>:LOOPFILTTER_RESET	set value for loop filter reset	Loop Reset	<SIM_prefix>:M:PRLMST:LoopReset:St
<prefix>:LED	readback value for blue/red/green LED	LED	<prefix>:PHASESHIFT	set value for additional phase shift		<SIM_prefix>:M:PRLMST	:LED:Rd	TODO
<prefix>:PHASEERR1	phase error before the phase shifter	RawPhiErr	<SIM_prefix>:M:PRLMST:RawPhiErr:Rd
<prefix>:PHASEERR2	phase error after the phase shifter	PhiErrFinal	<SIM_prefix>:M:PRLMST:PhiErrFinal:Rd
<prefix>:LOCK	lock logic status	LockLogicState	<SIM_prefix>:M:PRLMST:LockLogicState:Rd
<prefix>:INPUTMUX_RBV	readback input mux	Input MUX	<prefix>:LOOPFILTER_RESET_RBV	readback value for loop filter reset	LoopReset	<SIM_prefix>:M:PRLMST: LoopReset Input_MUX:Rd
<prefix>:	INPUTMUX	set	input mux	Input MUX		<SIM_prefix>:M:PRLMST:	Input_MUX:St
<prefix>:W0SCALE_RBV	readback w0 scale	w0_scale	<SIM_prefix>:M:PRLMST:w0_scale:Rd
<prefix>:LED	readback value for blue/red/green LED	W0SCALE	set w0 scale	w0_scaleLED	<SIM_prefix>:M:PRLMST:LEDw0_scale:RdSt	000: Error, FPGA image not flash, there should at least one LED on between Green and Red 001: Locked, but amplitude input is too low or high 010: Unlocked, but amplitude input is too low or high 011: Error, Locked and Unlocked should not be on in the same time 100: Error, there should at least one LED on between Green and Red 101: Locked, input amplitudes are good 110: Unlocked, input amplitudes are good 111: Error, Locked and Unlocked should not be on in the same time
<prefix>:W1_RBV	readback w1 value in radian	w1	<SIM_prefix>:M:PRLMST:w1:Rd
<prefix>:W1	set w1 value in radian	w1	<SIM_prefix>:M:PRLMST:w1:St
<prefix>:PRAMPSLOPE_RBV	readback value for phase shift ramp slope	Phase_ramp_gain	<prefix>:PHASEERR1	phase error before the phase shifter	RawPhiErr	<SIM_prefix>:M:PRLMST:RawPhiErrPhase_ramp_gain:Rd
<prefix>:PRAMPSLOPE	set value for phase shift ramp slope	Phase_ramp_gain	<SIM_prefix>:M:PRLMST:Phase_ramp_gain:St
<prefix>:ADCAMP0_RBV	readback value for ADC0 amplitude from CORDIC	ADC0_Amp	<SIM_prefix>:M:PRLMST:ADC0_Amp:Rd	LOLO: 0.4 LOW: 0.6 HIGH: 0 HIHI: 0
<prefix>:ADCAMP1_RBV	readback value for ADC1 amplitude from CORDIC	ADC1_Amp	<prefix>:PHASEERR2	phase error after the phase shifter	PhiErrFinal	<SIM_prefix>:M:PRLMST:PhiErrFinal:Rd	<prefix>:LOCK	lock logic status	LockLogicState	<SIM_prefix>:M:PRLMST:LockLogicState:Rd	<prefix>:INPUTMUX_RBV	readback input mux	Input MUX	0: Chan 1 - Chan 2 1: Chan 2 - Chan 1
<prefix>:INPUTMUX	set input mux	Input MUX	<SIM_prefix>:M:PRLMST:Input_MUX:St	0: Chan 1 - Chan 2 1: Chan 2 - Chan 1
<prefix>:W0SCALE_RBV	readback w0 scale	w0_scale	<SIM_prefix>:M:PRLMST:w0_scale:Rd	w0 scale register. w0 = 100Hz, this register is used to scale the w0 of the loopfilter. Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit. Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:W0SCALE	set w0 scale	w0_scale	<SIM_prefix>:M:PRLMST:w0_scale:St	w0 scale register. w0 = 100Hz, this register is used to scale the w0 of the loopfilter. Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit. Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:W1_RBV	readback w1 value in radian	w1	<SIM_prefix>:M:PRLMST:w1:Rd	w1 value in radian. Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit. Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:W1	set w1 value in radian	w1	<SIM_prefix>:M:PRLMST:w1:St	w1 value in radian. Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit. Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:PRAMPSLOPE_RBV	readback value for phase shift ramp slope	Phase_ramp_gain	<SIM_prefix>:M:PRLMST:Phase_ramp_gain:Rd	Slope of the phase shift ramp function. Internally converted to 18bit signed 2'comp value. Entered as a decimal in the GUI
<prefix>:PRAMPSLOPE	set value for phase shift ramp slope	Phase_ramp_gain	<SIM_prefix>:M:PRLMST:Phase_ramp_gain:St	Slope of the phase shift ramp function. Internally converted to 18bit signed 2'comp value. Entered as a decimal in the GUI
ADC1_Amp:Rd	LOLO: 0.4 LOW: 0.6 HIGH: 0 HIHI: 0	<prefix>:ADCAMP0_RBV	readback value for ADC0 amplitude from CORDIC	ADC0_Amp	<SIM_prefix>:M:PRLMST:ADC0_Amp:Rd	<prefix>:ADCAMP1_RBV	readback value for ADC1 amplitude from CORDIC	ADC1_Amp	<SIM_prefix>:M:PRLMST:ADC1_Amp:Rd
<prefix>:LOCKDISABLE_RBV	readback value for loop lock disable setting bit in lock logic state machine	LockDisable	<SIM_prefix>:M:PRLMST:LockDisable:Rd	ZSV: NO_ALARM OSV: MAJOR
<prefix>:LOCKDISABLE	set value for loop lock disable	LockDisable	<SIM_prefix>:M:PRLMST:LockDisable	:St
<prefix>:LOCKRESET_RBV	readback value for reset the lock logic state machine	StateReset	<SIM_prefix>:M:PRLMST:StateReset:Rd
<prefix>:LOCKRESET	set value for reset locking logic	StateReset	<SIM_prefix>:M:PRLMST:StateReset:St
LED_ADCAMPL				ZSV: MINOR OSV: NO_ALARM
LED_LOCK				ZSV: MAJOR OSV: NO_ALARM
LED_ERROR				ZSV: NO_ALARM OSV: MAJOR

SIM VCO (slave) PVs

...

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IOC names and PV prefixes

Frequency Locker PVs

MO DAC Control PVs

SIM FPGA MAC-IP mapping

PV names

Frequency Locker PVs

MO DAC Control PVs

MO RF-locking Matlab script PVs

MO RF-locking Matlab script PVs

Frequency Counter PVs

SIM PLL (master) PVs

SIM VCO (slave) PVs

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Page History

Versions Compared

Old Version 3

New Version Current

Key

Contents

IOC names and PV prefixes

Frequency Locker PVs

MO DAC Control PVs

SIM FPGA MAC-IP mapping

PV names

Frequency Locker PVs

MO DAC Control PVs

MO RF-locking Matlab script PVs

MO RF-locking Matlab script PVs

Frequency Counter PVs

SIM PLL (master) PVs

SIM VCO (slave) PVs