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The readout electronics for the 3x2 sensor module is split into two parts; the ASIC carrier with six detectors and the readout board with the FPGA, optical transceiver, power supplies and other supporting components. This page describe these parts in more detail. |
A GUI from Linear Technologies (now Analog Devices) called LTPowerPlanner has been used to calculate all the required currents and voltages in the system. It also calculates the estimated losses and efficiency of the system.
The system is designed to operate at an input voltage of 48 V, but can go as low as 30 V.
LTPowerPlanner | Datasheets |
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This system was initially designed to operate at an input voltage of 24 V to be compatible with the GT Readout Platform. It was abandoned in favor of the 48 V system above to make this 3x2 readout compatible with the upcoming SparkPix-S pixel detector, which has ~4x as many pixels in the same area and therefore needs almost double the analog power.
See Power supply modules and regulators page for details on interesting power supplies and regulators.
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The figures below give an approximation of where the power is consumed on the readout and ASIC carrier boards. The numbers are from the LTPowerPlanner block diagram above.
Readout board power map | Carrier board power map |
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DrawIO source file: power-maps.drawio |
Summary | Graphs |
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Running at 3.3V, see datasheet on restricted OneDrive for all values. Max power condition of 7.9 W (2.4 A @ 3.3 V) is used in the calculations below.
Analog | Digital and I/O | Analog test system | |
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Net | G_AS | G_DS | G_AS_2V5 |
Voltage | 1.3 V | 1.3 V | 2.5 V |
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
System requirement with 6 ASICs (+30% current for PVT variation) | 6*1.9*1.3 = 14.82 A +1.3 V @ 15 A 1.3*15 = 19.5 W | 6*0.5*1.3 = 3.9 A +1.3 V @ 4.0 A 1.3*4 = 5.2 W | 6*0.01*1.3 = 0.078 A +2.5 V @ 0.5 A 2.5*0.5 = 1.25 W |
Using worst-case values below for conservative estimate of the currents needed for the different supplies
Power supply rail | Part | Quantity | Max current |
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P0V85D | FPGA VCCINT/VCCINT_IO | 1 | 7 A |
Total: | 7 A | ||
P0V8D_ASIC | ASIC GT bias | 3*2 | < 0.1 A |
Total: | < 0.1 A | ||
P0V9D | FPGA MGTAVCC | 4 | 4 A |
Total: | 4 A | ||
P1V2D | FPGA MGTAVTT | 4 | 8 A |
Total: | 8 A | ||
P1V3D | SN74AXC4T774RSVR | 4 | 4*26 uA = 104 uA |
Total: | < 0.1 A | ||
P1V3D_ASIC[1..6] | ASIC digital and IO supply | 1 | 0.5*1.3 = 0.65 A |
Total: | < 0.7 A | ||
P1V8D | SN74AXC4T774RSVR | 4 | 4*26 uA = 104 uA |
SI5345A-D-GM | 1 | 260 mA | |
FPGA VCCAUX | 1 | ~500 mA | |
FPGA VCCAUX_IO | 1 | ~100 mA | |
FPGA MGTVCCAUX | 1 | ~300 mA | |
FPGA VCCO 0 | 1 | < 100 mA | |
FPGA XADC_VCC | 1 | ~10 mA | |
FPGA VCCO 64/65/66/70/71/91 | 1 | < 100 mA | |
MT25QU01GBBB8E12-0SIT | 1 | 55 mA | |
AD5541ABRMZ | 3 | < 1 mA | |
Total: | < 1.5 A | ||
P2V5D | XLL726371.428571I | 1 | 44 mA |
536FB156M250DG | 1 | 98 mA | |
AT24C64D-MAHM-T | 1 | 3 mA | |
FPGA VCCO 90 | 1 | < 100 mA | |
DS2411R | 2 | < 10 uA | |
Total: | < 0.3 A | ||
P3V3D | SI5345A-D-GM | 1 | 130 mA |
LMK61E2BAA-SIAT | 1 | 196 mA | |
FPGA VCCO 93/94 | 1 | < 50 mA | |
SN74AHC1G04DBVR | 3 | 3*4 = 12 mA | |
SN74LVC3G34DCUR | 3 | ~3*1 = 3 mA | |
LEAP transceiver | 1 | 2.4 A | |
Total: | < 3 A | ||
P1V3A_ASIC[1..6] | ASIC analog supply | 1 | 1.9*1.3=2.47 A |
Total: | < 2.5 A | ||
P2V5A_ASIC | ASIC analog test system | 6 | 6*10*1.3 = 78 mA |
Total: | < 0.1 A | ||
P3V3A | ADS1217IPFBT | 1 | 1.325 mA |
HIH-5031-001 | 1 | 0.5 mA | |
ADR360BUJZ | 1 | < 1 mA | |
ADR361BUJZ | 1 | < 1 mA | |
OPA2626IDGKR | 2 | 2*2*3.1 mA = 12.4 mA | |
AD5541ABRMZ | 2 | < 1 mA | |
MAX4781ETE | 4 | < 1 mA | |
Total: | < 0.1 A |
A GUI from Linear Technologies (now Analog Devices) called LTPowerPlanner has been used to calculate all the required currents and voltages in the system. It also calculates the estimated losses and efficiency of the system.
Power block diagram | LTPowerPlanner | Datasheets |
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Running at 3.3V, see datasheet on restricted OneDrive for all values. Max power condition of 7.9W (2.4A@3.3V) is used in the calculations below.
Analog
Digital and I/O
Analog test system
Net
G_AS
G_DS
G_AS_2V5
Voltage
1.3 V
1.3V
2.5 V
Required current per ASIC
1.85 A ≈ 1.9 A
0.468 A ≈ 0.5 A
0.01 A
System requirement with 6 ASICs
(+30% current for PVT variation)
6*1.9*1.3=14.82 A
+1.3 V @ 15 A
1.3*15=19.5 W
6*0.5*1.3=3.9 A
+1.3 V @ 4.0 A
1.3*4=5.2 W
6*0.01*1.3=0.078 A
+2.5 V @ 0.5 A
2.5*0.5=1.25 W
Using worst-case values below for conservative estimate of the currents needed for the different supplies
See Power supply modules and regulators page for details on interesting power supplies and regulators.
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Option B
New components
Separate ASIC supplies
Diagram
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Area
Cost
January 2024
Noise performance
±1% accuracy over line, load and temperature,
25 μVRMS output noise (10Hz to 100kHz)
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system/Os) are needed for the main blocks of the system and was used in the early design phases of the project to identify the number of pins needed for the connectors and the FPGA.
The FPGA has two types of GT quads:
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
From FPGA to PC:
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
Reverse calculation assuming the current PGPv4 running at 15 10 Gbit/s:
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview Clocks above for more details on the system clock structure.
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Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 | ||||||||||||
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TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | |
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C | ||||||||
Clock | |← | ← X → | →| | | X → | →| | | X → | →| | |||||||||||||||
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | ||
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
There is one GTY quad and one GTH quad left over.