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Introduction

The follow following discussions apply to the CSpad family of detectors, but all of the specific discussions and tests were done with the CSpad140k detector.  If, while reading this page, you would like to refer to the CSpad 2.3M or CSpad 140k configurations, an image of each configuration GUI screen is given at the bottom of this page in child pages.

Placing the integration window

Before going into detail, it is necessary to describe the pixel architecture of the cspad.  For this purpose, I have borrowed a figure from a paper presented at the SPIE conference by Philip Hart, et. al.

Holes generated by the incidence of the x-ray photons are collected at every pixel's charge sensitive amplifier. The resulting output voltage of this amplifier is then sampled and held for digitization.  The time during which the detector is sensitive to x-rays also known as integration window is established by the release of the reset switch on the input charge sensitive amplifier and then ended by the opening of the switch in for the sample and hold .  Holes resulting from the ejection of electrons by the incidence of the x-ray photons are collected on the capacitor in the sample and hold section during the integration window when the switch is closed.   The window ends when the switch is opened and then the amplifier is again reset.  After some time to allow the sample and hold output to settle, the external ramp input signal starts falling and the counter startstarts clocking.  When the levels match the external ramp level and the pixel signal level match, the comparator fires and the counter stops, giving resulting in the digital value for output .For the purposes of this discussion, many of the issues are neglected so that we can focus on the timing(single slope ADC principle).

All  parameters that affect the timing of the detector CSPAD detectors are clocked by the 125 MHzclock MHz clock with a cycle time of 8 nanoseconds except the "Run Delay" in the full CSpad 2.3M which is clocked at 119 MHz with a cycle time of 8.40336 nanoseconds.
The integration window includes the arrival of the FEL and is framed by the release of the amplifier reset and opening of the sample and hold switch. 
The duration of the integration window is determined by the "Int Time" parameter in the configuration.  A typical setting of 5000 gives commands an integration window of 40 microseconds.  To really understand the integration window we should look at the weighting function studies done by Sven Herrmann, Gabriella Carini, et. al. in various hutches at LCLS.

The weighting function shows the response at various flux levels vs time.  These curves are for a 40 microsecond integration window.  The 40 microsecond digital integration window starts with the command to release the amplifier reset, at -40 microseconds in the above curves.  Since we now use the analog reset, several microseconds elapse from the time we command the release of the reset and when some response is seen in the curves.  In the discussion below we are talking about the digital window, but remember that the actual performance off of the detector is determined by the curves show shown above.

Note also, that since the all the FPGA times start with a count of zero, we should addd add one to the settings before using them in calculations.

The position in time of the integration window relative to the event code 140 timing, is the sum of three things. 

The In the CSpad 140k, the position of the run trigger itself makes the first contribution.  We normally set it at 500 microseconds after the 140 event code. 

The second is the "Run Trig Delay" on the 140k and the "Run Delay" on the big CSpad 2.3M.  For the 140k it is typically has been 11020, or 88.168 microseconds. In the CSpad 2.3M, the "Run Delay" should include the 500 microseconds of the 140k run trigger, because there is no run trigger for the 2.3M.

These first two contributions are not part of the actual acquisition cycle, but determine the start of it.

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When the stale stand-alone evr issue raised it's head, CXI scientists scanned and then used these numbers.

500 400 + ((1102022580+1)*0.008) + ((280+1)*1.024) = 868.3912 microseconds, with a 40 microsecond window ending at 908.3912

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In both cases, the cycle time includes 3.125 milliseconds of unaccounted for time, that probably so far, some of which goes to transmitting the data, and is not configurablereading out the data.

The data readout time is related to "Read Clk Set", "Read Clk Hold" and "Row/Col Shift." Every block has to be read out serially: a total of 26x185 pixels for every pixel we have to clock 14 bits of data and do at least one row/col shift. So every pixel needs at least 14*(read_clock_set + read_clock_hold +2) + 2*(row/col_shift+1) + 4 clock cycles.

For the CSpad140k, "Read Clk Set" and "Read Clk Hold" values of 1 and "Row/Col Shift" value of 3:

(14*(1+1+2) + 2*(3+1) + 4) * 26 * 185 * 0.008 = 2616.64 microseconds, which still leaves 508.36 microseconds of undefined overhead in the cycle time.

For the CSpad 2.3M, because the data is read out over copper LVDS links, we need to use a "Read Clk Set" value of 2.

Timing for the DAQ trigger

Both detectors need a DAQ trigger to label events that the DAQ system wants to save.  All the timing of the integration window position depend only on the run trigger or the arrival of the specified event code.  The DAQ trigger only specified that the DAQ system wants this frame, so ti's arrival time is not critical.  The DAQ trigger must arrive after the run trigger, but no more than 500 microseconds after it.  The software looks at the configured delay of the run trigger, and adds 250 microseconds to that for the setting of the DAQ trigger delay.  This scheme means that you set the run trigger delay to set the position of the integration window and the set the DAQ trigger delay to the same value, so the software will place the daq trigger in the middle of the window.