...
- Run
iMPACT
from thebuild/firmware/<project>
directoryCode Block cd workspace/build/firmware/<project> impact
- 405: Select
Xilinx Flash/PROM
, click green arrow - 440: Select
BPI Flash Single FPGA
->Configure Single FPGA
, click green arrow - 405: Select
Platform Flash
forPROM Family
- 440: Select
Virtex 5
forTarget FPGA
405: Select {{Wiki Markup xcf32p
\[32
M
\]
}} for {{Device
(bits)
}}Wiki Markup - 440: Select {{
xcf128x
\[16
M
\]
}} for {{Storage
Device
(Bytes)
}} - Click
Add Storage Device
- Click green arrow
- Ignore
Checksum Fill Value
- Enter
Output File Name
(e.gv4-dpm.mcs
) - Select
Output File Location
File Format
:MCS
- 405:
Enable Revisioning
:No
- 405:
Enable Compression
:No
- 440:
Add Non-Configuration Data Files
:No
- Click
OK
- Pop-up:
OK
- Pop-up: Select
.bit
file:OK
Would you like to add another device to Revision: 0
:No
- Pop-up:
OK
- 440:
Multiboot blah, blah, blah
:Cancel
- Right click "
Generate File...
" (Deselect devices first by clicking on background)
- 405: Select
- There is no need to version control the
.mcs
file
...
- Ensure the JTAG dongle is connected to your board
- Verify the
esn
of the dongle - Log into the computer to which the dongle's USB cable is connected
- Run
iMPACT
from thebuild/firmware/<project>
directory- Load the project of interest or bail out of any pop-ups
- Select
Output
->Cable Setup...
- Ensure the JTAG dongle with your
esn
is selected - Click
OK
- Select the
Boundary Scan
window - For 405s:
- Right click on
PROM device
->Assign New Configuration File
- Select
.mcs
file ->Open
- PROM device now has file name instead of 'bypass'
- Right click on PROM device ->
Program
- Right click on
- For 440s:
- Right click on
FPGA device
->Add SPI/BPI Flash...
- Select
.mcs
file ->Open
Select {{Wiki Markup BPI
PROM
}}, {{XCF128X
}}, Data Width: {{16
}}, Select RS\[1:0\]b Pin Address Bits: {{NOT
USED
}}, {{OK
}}- Ignore iMPACT Warning by clicking
OK
- Right click on attached FLASH device ->
Program
- Right click on
- After completion, cycle board (or payload) power to reload the FPGA
...