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IOC nameCPU namePV prefix (<device>:<area>:<position>)Description

Location

Associated network nodesNotes
sioc-sys0-ms01cpu-sys0-sp01

FREQ:SYS0:00

SIM01 (SIM YCPSW PVs)

PRL:SYS0:1:MO

PVs for Master Oscillator in master source rack

  • SIM modules for freq. locker (SIM01)
  • Agilent freq. counter (FREQ:SYS0:00)
  • RF-locking Matlab script soft PVs (Charlie Xu, "LCLS2_MO_Frequency_locker_PID") (PRL:SYS0:1:MO:)
L2KG02-25

Freq. counter: freq-sys0-ms01

FPGA: 192.168.1.16


sioc-sys0-ms02cpu-sys0-sp01

PRL:SYS0:02 (SIM high-level PVs)

SIM02 (SIM YCPSW PVs)

PRL:SYS0:02:L0 (Beckhoff PA PVs)

PRL:SYS0:02:01 (Beckhoff rack PVs)

BKHF:SYS0:MS02 (Beckhoff low-level PVs)

PVs for SIM modules in master source rack and Beckhoffs in laser rack

  • SIM for L0-L1 PLL master (SIM02)
  • Beckhoff for:
    • L0-L1 VCO (slave) PA
    • L2CID-04 rack temp & water flow

L2KG02-24 (SIM)

L2CID-04 (Beckhoff)

Beckhoff: apc-sys0-ms02

FPGA: 192.168.1.20


sioc-sys0-ms03cpu-sys0-sp01

PRL:SYS0:03 (SIM Pvs)

SIM03 (SIM YCPSW PVs)

PRL:SYS0:03:L2 (Beckhoff L2 VCO PVs)

PRL:SYS0:03:L3 (Beckhoff L3 PVs)

PRL:SYS0:03:LO (Beckhoff LO PVs)

PRL:SYS0:03:01 (Beckhoff rack PVs)

BKHF:SYS0:MS03 (Beckhoff low-level PVs)

PVs for SIM modules in master source rack and Beckhoffs in LLRF rack

  • SIM for L2 PLL master (SIM03)
  • Beckhoff for:
    • L2 VCO (slave) PA
    • L3 PA
    • L3 LO PA
    • L2KG02-20 rack temp & water flow

L2KG02-24 (SIM)

L2KG04-20 (Beckhoff)

Beckhoff: apc-sys0-ms03

FPGA:  192.168.1.28


sioc-sys0-ms04cpu-sys0-sp01

PRL:SYS0:04:L0 (Beckhoff L0-L1 PVs)

PRL:SYS0:04:L2 (Beckhoff L2 PVs)

PRL:SYS0:04:LO (Beckhoff LO PVs)

PRL:SYS0:04:01 (Beckhoff L2KG02-24 rack PVs)

PRL:SYS0:04:02 (Beckhoff L2KG02-25 rack PVs)

BKHF:SYS0:MS04 (Beckhoff low-level PVs)

Pvs for Beckhoffs in master source rack*

  • L0-L1 return PA
  • L2 return PA
  • L0-L1 & L2 LO PA
  • L2KG02-24 rack temp & water flow
  • L2KG02-25 rack temp & water flow
* Separated from sioc-sys0-ms01 at HW engineer's request

L2KG02-24

L2KG02-25

Beckhoff: apc-sys0-ms04


sioc-sys0-ms05

cpu-sys0-sp01

PRL:SYS0:05 (SIM PVs)

SIM05 (SIM YCPSW PVs)

PVs for SIM modules in laser rack

  • SIM for L0-L1 PLL slave (SIM05)
L2CID-04FPGA: 192.168.1.19



sioc-sys0-ms06

cpu-sys0-sp01

PRL:SYS0:06 (SIM PVs)

SIM06 (SIM YCPSW PVs)

PVs for SIM modules in LLRF rack

  • SIM for L2 PLL slave (SIM06)
L2KG04-20FPGA:  192.168.1.24




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Frequency Locker PVs

MO DAC Control PVs

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PV nameDescription for PVRemarks (register name)YCPSW nameCalculaton Formula
<prefix>:SIMVERFirmware version number for MoFreqLocker ModuleVersion

<SIM_prefix>:M:MFL:Version:Rd


<prefix>:MODAC_RBVReadback value for DAC_OUTPUT3_REMOTE registerDAC_OUTPUT3_REMOTE<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:Rd

Value inside FPGA is a 18bit signed 2'comp value. 

MATLAB expect value to be a non-offset signed binary range from +/-(2^(18-1))

This value should not be displayed

  Instead, there should be a separate PV that converts this value, and map to +/-5V.

Because this is the real value that makes the most sense to any operators beside the developer

<prefix>:MODACVOLTDAC readout in VoltSoft PV [-5...+5V]

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

volt = Fixed1817toFloat(u) * 5.;

<prefix>:MODACSet value to DAC_OUTPUT3_REMOTE registerDAC_OUTPUT3_REMOTE

<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:St

Value inside FPGA is a 18bit signed 2'comp value. 

MATLAB expect value to be a non-offset signed binary range from +/-(2^(18-1))

This value should not be displayed

Because there is an MATLAB high level app running.  Only the readback value should be display

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