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As stated in the table, the detector has a 100um pixel pitch and can be configured in 5 different gain modes; 3 fixed gain modes and 2 auto-ranging gain modes. In the same way as for the ePix10k ASIC, the gain mode is selected using the tr_bit register and the pixel map settings. The combinations to get to the specific gain modes can be seen in table 3.

Table 2. Tr_bit and pixel config file combinations are required to get a specific gain mode.

As with the other members of the ePix family of detectors, the analogue analog chain consists of a CSA with a switched reset scheme, a 1st order low pass filter, and a correlated double sampler. The CSA has been designed with the option to vary the feedback capacitance of the CSA, effectively changing the gain of the systempixel array size for the ASIC is 192x144, however, since only a small sensor is used for the prototype, only 48x48 pixels are bonded to a sensor.

Figure 3. Analogue channel layout for the ePixHR5kHz pixel.

The pixel array size for the detector is 192x144. Figure 2 show a depiction of the ASIC layout with core blocks highlighted.

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Figure 2. Image of the ASIC functional blocks.

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In the initial testing of this camera, the firmware used a single trigger scheme to read out the events. Due to resulting baseline instability, this was changed to a dual trigger system, where the DAQ trigger controls at what frequency the frames are read out, and the Run trigger decided at what frequency the ASIC is being run. As such, if the run trigger is set to 5kHz, and the DAQ trigger to 120Hz, then we only read out an event every 8ms. The idea is to have the ASIC always run at a set frame rate, to ensure thermal (baseline) stability, while we can change the readout rate to match the pulse arrival frequency of the beam. We still need to verify that the new trigger scheme works. The timing diagram for the readout of the ePixHR5kHz ASIC can be seen in Figure 4.

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Figure 4. The timing diagram for the pixel readout for the ePixHR5kHz.

The trigger arrival (run trigger) is located at the starting point on the left. Both the R0delay and ACQ delay are tied back to the trigger. The R0delay gives the time from the trigger arriving until the CSA is taken out of reset and start integrating the charge from the sensor. The ACQdelay gives the time from the trigger until the ACQ goes high and the first sampling of the CDS takes place. The second CDS sampling takes place at the end of the ACQ window. As such, the RO window, also referred to as the baseline integration is set by ACQdelay-R0delay, while the ACQ window, also referred to as the signal integration, is set by the ACQwidth. The ACQWidth starts form the end of the ACQ delay.

The SROdelay sets the time from the end of the ACQ window until the readout starts. Once the SRO signal goes high, the readout starts and the conversion time needed fully read out the collected values is dictated by the number of rows the ADC is reading out, and the SERDES clocking frequency used, as described here.

The additional time needed in this readout scheme to reset the channel (CSA and CDS) is yet to be experimentally determined but is currently assumed to be in the 3-4 us range.

All the registers above are stated as units of 10ns. As such, setting ACQwidth to 2400 gives an ACQ (signal) integration window of 24 us

A first evaluation of the gains for the high and low gains, as well as the ratio between the two, can be seen in Table 3. It should be noted that this was measured using v2 of the ASIC, the original single trigger firmware, 262MHz Serdes clock, symmetrical ACQ/RO widths (24us), and a 4kHz frame rate. This measurement has to be redone and validated for v4 of the ASIC, with the final settings and firmware.

Table 3. Initial measurements for the FH and FM gains.