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The weighting function shows the response at various flux levels vs time.  These curves are for a 40 microsecond integration window.  The 40 microsecond digital integration window starts with the command to release the amplifier reset, at -40 microseconds in the above curves.  Since we now use the analog reset, several microseconds elapse from the time we command the release of the reset and when some response is seen in the curves.  In the discussion below we are talking about the digital window, but remember that the actual performance of the detector is determined by the curves show shown above.

Note also, that since the all the FPGA times start with a count of zero, we should add one to the settings before using them in calculations.

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When the stale stand-alone evr issue raised it's head, CXI scientists scanned and then used these numbers.

500 400 + ((1102022580+1)*0.008) + ((280+1)*1.024) = 868.3912 microseconds, with a 40 microsecond window ending at 908.3912

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For the CSpad 2.3M, because the data is read out over copper LVDS links, we need to use a "Read Clk Set" value of 2.