ERROR: Unable to STOP PowerPC Processor
Check: (1) If the FPGA is Configured Correctly (or)
(2) If Processor Reset and Clock Ports are Connected Correctly
C103 scraped off.
2-4
00000019B108
08:00:56:00:42:XX
917
prod 2.2, 927M
rescue 2.2, 927M
120503
Programming f/w took two attempts; XMD 'dow'ing devel and 'con'ing causes crash to 0x700. XMD gives:
Code Block
ERROR: Unable to STOP PowerPC Processor
Check: (1) If the FPGA is Configured Correctly (or)
(2) If Processor Reset and Clock Ports are Connected Correctly
C76 and R22 scraped off.
2-5
00000019A827
08:00:56:00:42:f5
917
0.8.0
prod 2.2, 927M
rescue 2.2, 927M
120503
OK
2-6
00000019C145
08:00:56:00:42:fa
917
prod 2.2, 1088:1104
rescue 2.2, 1088:1104
120531
OK
2-7
00000019D013
08:00:56:00:42:f8
917
prod 2.2, 1088:1104
rescue 2.2, 1088:1104
120531
OK
2-8
000000196E67
Bad. XMD gives:
Code Block
ERROR: Unable to STOP PowerPC Processor
Check: (1) If the FPGA is Configured Correctly (or)
(2) If Processor Reset and Clock Ports are Connected Correctly
2-9
08:00:56:00:42:f4
917
prod 2.2, 927M
rescue 2.2, 927M
120503
OK
2-10
00000019DC05
08:00:56:00:42:fb
917
prod 2.2, 927M
rescue 2.2, 927M
120503
OK
2-11
000000197D2F
08:00:56:00:42:XX
120503
Mark says board is bad. XMD gives:
Code Block
ERROR: Unable to STOP PowerPC Processor
Check: (1) If the FPGA is Configured Correctly (or)
(2) If Processor Reset and Clock Ports are Connected Correctly
