• Created by Unknown User (phansson), last modified on Feb 22, 2015

Logbook

Full SVT DAQ test run log

2015-02-05

Unpacking, prepping EEL clean room space.

2015-02-06

SVT box installed. Ready to install U-channels.

LV and HV cables unpacked and run from MPOD to flange. LV cables ohmed out at MPOD end with FEB

FEB chiller connected to manifold and tested.

Got ATCA crate from hall.

2015-02-07

MPOD power checked without sense and no detector connected.

MPOD EPICS interface tested, using the IOC on the Hall-B commuters (clonioc1). 

5:00pm
1st power test of the front end boards on the plate without any link. All currents look good.
Layer, DVDD, AVDDP, AVDDN
L1t 0.987, 0.892, 0.249
L2-3t 0.974, 0.902, 0.251
L5t 0.965, 0.882, 0.253
L6t 0.978, 0.884, 0.248
L4t 0.987, 0.889, 0.244
L4b 0.962, 0.869, 0.255
L5b 0.981, 0.875, 0.250
L6b 0.972, 0.875, 0.253
L1b 0.985, 0.876, 0.245
L2-3b 0.959, 0.877, 0.256

5:10pm
Omar found that one of the LV mezzanine card (L5t, bottom screw) was now connecting AGND to the FEB support plate. After debugging turns out that it was the edge of the high-speed mSAS cables that was conducting and touching components on the FEBs.  

TKN - my notes on this

  • Omar found flaky short to plate on one FEB
  • Investigation revealed edges of data cables could short to components and/or mounting screws 
  • Ryan reminded us that the data cable shield is connected to ground in the cable (and thus to FEB ground).  So, likely that a cable edge was simply touching nearby screw.
  • All data cables passivated alongside FEB cooling plate as per note 7 on cable data sheet (doh!)

5:30pm
L4t and L4b power was swapped on the back of the breakout box (on the flange side). For reference this is patch panel P3 and thus S1 and S2 where swapped. Mapping power to FEBs is ok now.

12:45pm
Wrapped all mSAS cables with kapton tape. Only wrap the parts that cover the FEB plate plus a little extra. The other side needs to be protected by a sleeve, e.g. Halar. 

2015-02-08

* All FEB's sync all hybrids!

====================================================
Physical FEB: 1t Serial: FebFpga: 11 Control/Data Fiber D/H Flange: 3
====================================================
DPM 7, DP 0, Hybrid 3, All sync fine
DPM 7, DP 1, Hybrid 2, All sync fine
DPM 7, DP 2, Hybrid 1, All sync fine
DPM 8, DP 0, Hybrid 0, All sync fine
====================================================

====================================================
Physical FEB: 2-3t Serial: FebFpga: 2 Control/Data Fiber C/G Flange: 2
====================================================
DPM 11, DP 0, Hybrid 3, All sync fine
DPM 11, DP 1, Hybrid 2, All sync fine
DPM 11, DP 2, Hybrid 1, All sync fine
DPM 12, DP 0, Hybrid 0, All sync fine
====================================================

====================================================
Physical FEB: 4t Serial: FebFpga: 6 Control/Data Fiber A/E Flange: 0
Physical FEB: 4t Serial: FebFpga: 1 Control/Data Fiber C/G Flange: 2 (after switch)
====================================================
DPM 12, DP 1, Hybrid 3, All sync fine
DPM 12, DP 2, Hybrid 2, All sync fine
DPM 13, DP 0, Hybrid 1, All sync fine
DPM 13, DP 1, Hybrid 0, All sync fine
====================================================
* Connected high speed cable and powered up. The currents are as follows:
- DIGI: 1.129 A
- ANAP: 1.207 A
- ANAN: .231
* The FEB has a control link but it has several errors. The high speed cable
needs to be switched to a different flange channel.
* Switching the on the flange card didn't resolve the control link errors
present on the flange channel.
* Switched the high speed cable to Flange 2 and control link was fine
====================================================

====================================================
Physical FEB: 5t Serial: FebFpga: 7 Control/Data Fiber A/E Flange: 0
====================================================
DPM 5, DP 1, Hybrid 3, All sync fine
DPM 5, DP 2, Hybrid 2, All sync fine
DPM 6, DP 0, Hybrid 1, Initially saw no sync, after power cycling and
switching hybrids at the crossover, all sync fine.
All that was really required was a power cycle.
DPM 6, DP 1, Hybrid 0, All sync fine
====================================================
* Connected high speed cable and powered up. The currents are as follows:
- DIGI: 1.112 A
- ANAP: 1.173 A
- ANAN: .257
* Connected the hybrids and tried to run through CODA. Ran into the
same issues as before where we can't connect to the DPM's when not
logged in as Ryan.
====================================================

====================================================
Physical FEB: 6t Serial: FebFpga: 8 Control/Data Fiber A/E Flange: 0
====================================================
DPM 4, DP 0, Hybrid 3, All sync fine
DPM 4, DP 1, Hybrid 2, All sync fine
DPM 4, DP 2, Hybrid 1, All sync fine
DPM 5, DP 0, Hybrid 0, All sync fine
====================================================

====================================================
Physical FEB: 1b Serial: FebFpga: 9 Control/Data Fiber D/H Flange: 3
====================================================
DPM 10, DP 0, Hybrid 3, All sync fine
DPM 10, DP 1, Hybrid 2, All sync fine
DPM 10, DP 2, Hybrid 1, All sync fine
DPM 9, DP 2, Hybrid 0, All sync fine
====================================================

====================================================
Physical FEB: 2-3b Serial: FebFpga: 0 Control/Data Fiber C/G Flange: 2
====================================================
DPM 10, DP 3, Hybrid 3, All sync fine
DPM 12, DP 3, Hybrid 2, All sync fine
DPM 13, DP 2, Hybrid 1, All sync fine
DPM 8, DP 3, Hybrid 0, All sync fine
====================================================

====================================================
Physical FEB: 4b Serial: FebFpga: 5 Control/Data Fiber B/F Flange: 1
====================================================
DPM 0, DP 0, Hybrid 3, All sync fine
DPM 0, DP 1, Hybrid 2, All sync fine
DPM 0, DP 2, Hybrid 1, All sync fine
DPM 1, DP 0, Hybrid 0, All sync fine
====================================================
* After power up, tried to write config and there was an error. Power
cycling the FEB didn't help. Restarting the control
server fixed the issue.
====================================================

====================================================
Physical FEB: 5b Serial: FebFpga: 4 Control/Data Fiber B/F Flange: 1
====================================================
DPM 1, DP 1, Hybrid 3, All sync fine
DPM 1, DP 2, Hybrid 2, All sync fine
DPM 2, DP 0, Hybrid 1, All sync fine
DPM 2, DP 1, Hybrid 0, All sync fine
====================================================
* Connected high speed cable and powered up. The currents are as follows:
- DIGI: 1.120 A
- ANAP: 1.160 A
- ANAN: .254
====================================================

====================================================
Physical FEB: 6b Serial: FebFpga: 3 Control/Data Fiber B/F Flange: 1
====================================================
DPM 2, DP 2, Hybrid 3, All sync fine
DPM 3, DP 0, Hybrid 2, All sync fine
DPM 3, DP 1, Hybrid 1, All sync fine
DPM 3, DP 2, Hybrid 0, All sync fine
====================================================

2015-02-10

Installed front end board plate and connected detector.
Issues:
1) one the patch panel connectors had two pins bent. One was touching the shell and effectively grounding the feb cooling plate to the vacuum box.
2) the lugs on the power flange were accidentally touching the vacuum box.

The two pins were on AVDD. They were bent back and connector plugged in. Power look fine. We are redundant since all avdd pins share connections at the power flange board anyway. May want to inspect connector/pins at some point.

Checked power to all FEB after installation and they all look fine.

SVT chiller connected, filled, run. Fill level is just above 3/4 (highest non-alarm level). There is a little bit of coolant left in the plastic jug, plus three unopened bottles.

TKN - a longer exposition on the above:

  • FEB plate in - is cable clip in back really advisable?
  • must remember order: L46 hybrids, L46 data, L13 hybrids, L13 data
  • connected patch panel
  • connect flange to data last
  • lessons:
    • connection order: P4, P2, P3, HV2, HV2, P5, P1 ?
    • gentle with Dsubs!!
Found several ground faults:
  • Data cables were contacting flange and therefore shorting the following path:  Vacuum box -> mini-SAS shield -> mini-SAS ground -> FEB ground -> hybrid ground -> SVT detector ground (module, u-channel, box).  This is bad. 
  • Placed temporary mylar cone in flange.
  • Realized that bundling data cables will create flaky shorts among all FEB grounds.  Will need to passivate data cables over nearly their entire length in some way.
  • Found new short between SVT Box and Flange: ground lug on inside of flange meant for grounding the SVT was touching the flange.  Ground lugs have been covered in Kapton tape. Question: do we intend to use these?
  • Found short between FEB plate and SVT Box. Pins inside P4 were bent during connection and ground pin was bent into shell. This shorts the following path: FEB plate -> Patch panel -> connector shell -> FEB ground -> hybrid ground -> SVT detector ground (module, u-channel, Box).
  • Pins are redundant.  Pins were bent back into position as well as possible. Lower left pin has slight s-curve but pushed partway into pin block. Upper left pin has larger s-curve.  Both appeared to engage after repair but should be replaced.

2015-02-11

Before attempting to take data, all of the FEB's were checked for sync.  The results are as follows: 

Summary: All APV's sync.

==============================================================
Physical FEB: 1t Serial: FebFpga: 2
Device DNA: 0x14084072beb01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 11, DP 0, Hybrid N/A, N/A
DPM 11, DP 1, Hybrid N/A, N/A
DPM 11, DP 2, Hybrid 1, all sync
DPM 12, DP 0, Hybrid 0, all sync
==============================================================

==============================================================
Physical FEB: 2-3t Serial: FebFpga: 0
Device DNA: 0x42084072beb01400
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 10, DP 3, Hybrid 3, all sync, APV 3 base value is lower than usual ~0x5f7
DPM 12, DP 3, Hybrid 2, all sync, APV 2 base value is lower than usual ~0x5de
DPM 13, DP 2, Hybrid 1, all sync, APV 2 base value is lower than usual ~0x525
DPM 08, DP 3, Hybrid 0, all sync
==============================================================

==============================================================
Physical FEB: 4t Serial: FebFpga: 5
Device DNA: 0x58d04072beb01400
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 0, DP 0, Hybrid 3, all sync
DPM 0, DP 1, Hybrid 2, all sync
DPM 0, DP 2, Hybrid 1, all sync
DPM 1, DP 0, Hybrid 0, all sync
==============================================================

==============================================================
Physical FEB: 5t Serial: FebFpga: 8
Device DNA: 0x52814100a1b01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 4, DP 0, Hybrid 3, all sync, APV 1 and 4 base value is lower than usual
DPM 4, DP 1, Hybrid 2, all sync
DPM 4, DP 2, Hybrid 1, all sync, APV 3 base value is lower than usual
DPM 5, DP 0, Hybrid 0, all sync, APV 0 and 4 base value is lower than usual
==============================================================

==============================================================
Physical FEB: 6t Serial: FebFpga: 7
Device DNA: 0x50814100a1b01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 5, DP 1, Hybrid 3, all sync
DPM 5, DP 2, Hybrid 2, all sync
DPM 6, DP 0, Hybrid 1, all sync
DPM 6, DP 1, Hybrid 0, all sync
==============================================================

==============================================================
Physical FEB: 1b Serial: FebFpga: 9
Device DNA: 0x24d04072beb01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 10, DP 0, Hybrid N/A, N/A
DPM 10, DP 1, Hybrid 1, all sync
DPM 10, DP 2, Hybrid 0, all sync
DPM 09, DP 2, Hybrid N/A, N/A
==============================================================

==============================================================
Physical FEB: 2-3b Serial: FebFpga: 11
Device DNA: 0x02d04072beb01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 7, DP 0, Hybrid 3, all sync
DPM 7, DP 1, Hybrid 2, all sync
DPM 7, DP 2, Hybrid 1, all sync
DPM 8, DP 0, Hybrid 0, all sync
==============================================================

==============================================================
Physical FEB: 4b Serial: FebFpga: 1
Device DNA: 0x72814100a1b01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 12, DP 1, Hybrid 3, all sync
DPM 12, DP 2, Hybrid 2, all sync
DPM 13, DP 0, Hybrid 1, all sync, APV 0 base value is lower than usual
DPM 13, DP 1, Hybrid 0, all sync
==============================================================

==============================================================
Physical FEB: 5b Serial: FebFpga: 4
Device DNA: 0x1c084072beb01400
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 1, DP 1, Hybrid 3, all sync
DPM 1, DP 2, Hybrid 2, all sync
DPM 2, DP 0, Hybrid 1, all sync
DPM 2, DP 1, Hybrid 0, all sync, APV 3 base value is lower than usual
==============================================================

==============================================================
Physical FEB: 6b Serial: FebFpga: 3
Device DNA: 0x70d04072beb01c00
FpgaVersion: 0xb0000024
Control/Data Fiber: Flange:
==============================================================
DPM 2, DP 2, Hybrid 3, all sync
DPM 3, DP 0, Hybrid 2, all sync
DPM 3, DP 1, Hybrid 1, all sync, APV 2 base value is lower than usual
DPM 3, DP 2, Hybrid 0, all sync
==============================================================

Hacked coda to run from ppa-pc91245.

Run 837, L4t, bias to H2 and H3 (some issue with mpod crate), 
Run 838, L4t, bias to all four hybrids.

Run 840, full detector, ET ring adjusted for large events. Note that there was an error on dpm7 when I hit "Go" (something with FebCore). Things looked ok and DTM0 say Ack on all dpm's.

SVT chiller flow switch tested. Drained and refilled chiller in the process; level is just above 3/4, jug is empty. Chiller is running at stage 3 (we got a pressure trip at stage 4, which has not happened before - not sure why); this will be our normal setting. Estimated flow (based on pressure drop vs. flow switch trip) is 1.5 GPM. SVT chiller is connected to Wesley's EPICS stuff; work in progress.

2015-02-12
  • FEB chiller setup simplified so we just have the flow meter and flow switch (no manifold). This will make it easier to swap hoses or add components if we decide to do that before installation. Flow is unchanged at ~5 GPH (bottom of the flow meter range, below the flow switch range).
  • Noise performance results of first full test with all FEB's and hybrids powered on and biased.  Only a single COB was setup to run with CODA.  Overall, the noise on all FEB's that we took data with looked as expected.

==============================================================
Physical FEB: 4t Serial: FebFpga: 5
==============================================================
Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 2: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 0: Looks fine. Noise ~51 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
==============================================================

==============================================================
Physical FEB: 5t Serial: FebFpga: 8
==============================================================
Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 6t Serial: FebFpga: 7
==============================================================
Hybrid 3: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~52 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 5b Serial: FebFpga: 4
==============================================================
Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~49 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 6b Serial: FebFpga: 3
==============================================================
Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
==============================================================

  • Added the rest of the DPM's (dpm's 8-14)  and DTM 1 to the coda database.  Tried running but encountered several coda related problems along the way.

2015-02-13

Plan for next weekend:
  • Remove data flange and disconnect all cables.  Mark out desired lengths and passivation locations for all data cables. Clear all cables to inside of vacuum box for power flange removal.
  • Disconnect patch panel. Remove power flange.  Implement final grounding scheme on power flange.
  • Remove all data cables for passivation and/or replacement.  Fold and passivate data cables.
  • Install temporary lever support.  Disconnect linear shifts and flex pivots.  Remove linear shifts. Disconnect cooling and remove cooling feedthroughs.
  • Release vacuum box from top clamp. Remove cooling manifold. Remove vacuum box for packing.
  • Pull FEB cooling plate out as far as L1-3 allows. Remove P4 male DB44 from patch panel and cut all zip ties on those wires. Remove L4b LV mezzanine, if necessary. Replace lower-left pin and re-insert.  If pin doesn’t push in, then replace upper-left pin.  Otherwise; extract and mark all pins, replace upper left pin, reinsert all pins in new shell.  Reinstall P4 on patch panel.  Push cooling plate back into SVT box.  Use clamp to lock patch panel into SVT box. Use zip ties to lock lever lock into place?
  • Re-install L4-6 data cables. Re-install L1-3 data cables, if possible. 
  • Install hall probe in L6 electron-side window with DP190 and tape wire into place.
  • Secure loose data cables in SVT box. Tape foil to box from crane straps.
  • Lock lever lock into box for safety with clamp.
  • Lock L46 upper hanger with jam nut!
  • Blow out cooling lines.
  • Prepare G10 pieces for SVT isolation.
  • Pack all needed items to take to Hall B for installation.
  • Prepare straps and tie-downs for lifts on Monday.
  • Move DAQ to Hall B and set up on network.
Plan for Monday:
  • Wipe down shipping plate from larger box and take into cleanroom on dollies. Lay foil along shipping plate for bottom of box. (15")
  • Release SVT from table.
  • Crane SVT onto shipping plate. (15")
  • Wrap and tape SVT box with foil. (15")
  • Roll SVT out of cleanroom. Cinch SVT down to shipping plate with tie downs. (15”)  *1’*
  • Install lid on inner box. (15")
  • Roll SVT out to crane area. (15")
  • Crane SVT into outer box.  Install foam. (15")
  • Close outer box. (15")
  • Crane outer box onto truck, levers facing rear, along with vacuum box and large crate with other items. (30”) *2’15”*
  • Slow truck move into Hall B down ramp. (30")
  • Crane inner box out. (15”) *3’*
  • Open inner box. (15")
  • Crane SVT up to pie tower on shipping plate. (15")
    • Pull SVT in and lower onto lift cart.
  • Move SVT to PS magnet (15")
    • Slow roll on lift cart to alcove.
    • Release SVT from shipping plate.
    • Transfer to lift cart/table in alcove.
    • Lift up on cart, then shoulder-height lift to table in front of vacuum chamber.
  • Get SVT into position to transfer to vacuum chamber (15”) *4’*
  • Transfer SVT to vacuum chamber. (15”) *4’15*
  • Isolate SVT box with G10 (15’)
  • Align SVT and lock into place (120")
Questions:
  • How heavy is the SVT?  Can we avoid the first crane lift with a manual lift?
  • Can we do to alignment on Day 1?

 

  • Noise performance results from run 855 with all dpms.  Noise looks as expected for all hybrids. 

==============================================================
Physical FEB: 1t Serial: FebFpga: 2
==============================================================
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels.  Noise looks slightly higher but it's hard to tell
Hybrid 1: Looks fine. Noise ~55 ADC Counts, high noise on edge channels.  
==============================================================

==============================================================
Physical FEB: 2-3t Serial: FebFpga: 0
==============================================================
Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~54 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~52 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 4t Serial: FebFpga: 5
==============================================================
Hybrid 3: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 5t Serial: FebFpga: 8
==============================================================
Hybrid 3: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 6t Serial: FebFpga: 7
==============================================================
Hybrid 3: Looks fine. Noise ~53 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~54 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~53 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 1b Serial: FebFpga: 9
==============================================================
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~53 ADC Counts, high noise on edge channels and noise rise on APV 0  
==============================================================

==============================================================
Physical FEB: 2-3b Serial: FebFpga: 6
==============================================================
Hybrid 3: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 4b Serial: FebFpga: 1
==============================================================
Hybrid 3: Looks fine. Noise ~52 ADC Counts, high noise on edge channels 
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

=============================================================
Physical FEB: 5b Serial: FebFpga: 4
==============================================================
Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~49 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 6b Serial: FebFpga: 3
==============================================================
Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
==============================================================

  •  The SVT Gui was updated such that FebFpga 11 is now mapped to FebFpga 6.  This was needed in order for the EPICS hybrid and FEB temperature GUI's to function properly. 
  • A "power all" button was added to the hybrid GUI
  • FEB 23b and 5t were loaded with new firmware.  Data with these two boards will be taken tomorrow.  If the baseline and noise are found to be unreasonable, all boards will be flashed with the new firmware.

2015-02-15

  • The remaining (8) FEB's were flashed with firmware image 0xD0000000.  Ben or Ryan can provide a list of fixes/improvements that this version of the firmware contains.
  • The FEB's were powered on, and the links were all checked.  A large amount of errors were immediately seen on  DPM 3/Data Path 0-2 and DPM 0/Data Path 0.  The first group of links that had errors were all associated with the same FEB.  It's harder to tell if this is the case with the errors on DPM 0/Data Path 0.
  • Two fibers  (F & H)  were switched at the back of the COB in order to check if the link errors followed the DPM.  After the switch, the link errors were observed on DPM 10/Data Path 0-2.  This is where they were expected to appear if the errors were due to something downstream of the DPM.  This eliminated the DPM as being the cause of the link errors.
  • After switching the fibers at the back of the COB back to their original position, the same fibers were switched at the flange.  Once again, the errors showed up on DPM 10/DP 0-2.  This eliminated the fibers from being the problem.
  • The problematic links were then traced to FEB 6b.  In order to check if the problem was originating upstream of the FEB's, high speed cables 6b and 6t were switched. This was done through the side windows on the SVT box and was relatively easy to do. When this was done, the errors began to appear on DPM 5/6, which were the DPM's that were connected to 6t before the switch.  This seems to indicate that the link problems were originating from the FEB and not upstream.  We switched back the high speed cables to their original state.
  •  Finally, we switched the high speed cables connected to 6b and 6t at the flange.  Once again, we saw the same behavior observed during 5 above. This confirms that the link errors were being generated by the FEB's.
  • The system was let run for a few hours and the links were logged in order to check long term stability.


2015-02-16

New GUI to check hybrid sync status is now active:  svtHybSync.adl. 
It now contains information about the sync status for the FEBs. It looks like it’s working: I can see that the powered FEB right now has sync 0x0 for all data paths. The other don’t have a “valid xml” which make sense. We can change the error codes later. Please look at this and tell me if this status corresponds to what your expect. Below the sync I have information about the data DPM’s. It will allow us to see the status and configuration of all DPM’s. I’m also adding the link errors to this GUI. It works but I have turned it off now as it’s too slow. I’ll be working on that tomorrow morning. (Pelle)

2015-02-23

Updated to SVT DAQ epics. Check out instruction on  EPICS Instructions. We are now running 14 data dpm , 1 control dpm and 2 dtm control IOCs in parallel.
Added FebNum/HybNum and run state monitoring in "svtHybSync.adl" GUI from data dpm to check mapping.
Added new GUI svtDataDpmLinkStatus.adl GUI to monitor link error. Got the RxFrameErrorCount implemented so far.


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