L0M16 Half-Module

20190412
L0M16 Half Module pretest after pinholes pulled

High Voltage Test
(V) (uA)
V:D/I:D
50 0.32
100 0.49
200 0.71
300 0.94
386 20.08

Low Voltage Test
(V) (A)
V:D/I:D
Pre-Config
AVDD: 2.50 0.107
DVDD: 2.50 0.240
V125: 1.25 0.000

Post-Config
AVDD: 2.50 0.261
DVDD: 2.50 0.245
V125: 1.25 0.234

Bad Channel Table
Sector B Sector A
pCH | apvCH | 128+apvCH | 2*128-apvCH-1| 128-apvCH-1
APV0
0 | 0 | 128 | 255 | 127
APV1
204 | 76 | 204 | 179 | 51
220 | 92 | 220 | 163 | 35
APV2
348 | 92 | 220 | 163 | 35
APV3
384 | 0 | 128 | 255 | 127
401 | 17 | 145 | 238 | 110
406 | 22 | 150 | 233 | 105
511 | 127 | 255 | 128 | 0
Nlow: 8

Baseline_config Noise at 0V bias:

Baseline_config Noise and icalScan 45 cg0 at 50V bias:

Tests after being put into Module 2 Stereo:

High Voltage Test

(V) (uA)

V:D/I:D

50  0.17

100  0.30

150  0.39

200  0.46

250  0.55

300  2.40