| Name | Description | Group | Access | log base 2 of size | Address | bit width | signed/unsigned |
|---|---|---|---|---|---|---|---|
test | for testing read/write | debug | rw | 0 | 0 | 20 | unsigned |
banyan_mask | active channels for spurs waveforms | rw | 0 | 1 | 8 | unsigned | |
banyan_reset | trigger a new spurs waveform read | w | 0 | 2 | 1 | unsigned | |
banyan_status | banyan spurs waveform status bit 30: new data ready | r | 0 | 3 | 32 | unsigned | |
buf_trig | w | 0 | 4 | 1 | unsigned | ||
keep | Active channel bitmask for "trace data" | w | 0 | 5 | 32 | unsigned | |
llspi | rw | 0 | 6 | 9 | unsigned | ||
trace_reset | Signal "trace data" to get new data | w | 0 | 7 | 1 | unsigned | |
trace_status1 | "trace data" status: bit 30: new data ready | r | 0 | 8 | 32 | unsigned | |
trace_status2 | r | 0 | 9 | 32 | unsigned | ||
trig_internal | w | 0 | 10 | 1 | unsigned | ||
llspi_status | r | 0 | 19 | 8 | unsigned | ||
llspi_result | r | 0 | 20 | 8 | unsigned | ||
clkcnt | r | 0 | 21 | 32 | unsigned | ||
frequency_4xout | r | 0 | 22 | 32 | unsigned | ||
frequency_adc | r | 0 | 23 | 32 | unsigned | ||
frequency_clkout3 | r | 0 | 24 | 32 | unsigned | ||
frequency_dac_dco | r | 0 | 25 | 32 | unsigned | ||
U15_spi_start | w | 0 | 26 | 1 | unsigned | ||
U15_spi_read | w | 0 | 27 | 1 | unsigned | ||
U15_spi_addr | w | 0 | 28 | 16 | unsigned | ||
U15_spi_rdbk | r | 0 | 29 | 16 | unsigned | ||
U15_spi_ready | r | 0 | 30 | 1 | unsigned | ||
U15_sdo_addr | r | 0 | 39 | 8 | unsigned | ||
U15_spi_data | w | 0 | 40 | 16 | unsigned | ||
sync_ad7794_cset | w | 0 | 31 | 10 | unsigned | ||
sync_tps62210_cset | w | 0 | 32 | 6 | unsigned | ||
U18_spi_start | w | 0 | 33 | 1 | unsigned | ||
U18_spi_read | w | 0 | 34 | 1 | unsigned | ||
U18_spi_addr | w | 0 | 35 | 8 | unsigned | ||
U18_spi_rdbk | r | 0 | 36 | 24 | unsigned | ||
U18_spi_ready | r | 0 | 37 | 1 | unsigned | ||
U18_sdo_addr | r | 0 | 38 | 1 | unsigned | ||
U18_spi_data | w | 0 | 41 | 24 | unsigned | ||
U2_clk_reset | w | 0 | 42 | 1 | unsigned | ||
U3_clk_reset | w | 0 | 43 | 1 | unsigned | ||
U2_dout | r | 0 | 44 | 64 | unsigned | ||
U3_dout | r | 0 | 46 | 64 | unsigned | ||
idelayctrl_reset | w | 0 | 48 | 1 | unsigned | ||
U2_iserdes_reset_r | w | 0 | 49 | 1 | unsigned | ||
U3_iserdes_reset_r | w | 0 | 50 | 1 | unsigned | ||
U4_reset_in | rw | 0 | 51 | 1 | unsigned | ||
scanner_scan_trigger | w | 0 | 52 | 1 | unsigned | ||
scanner_autoset_enable | w | 0 | 53 | 1 | unsigned | ||
scanner_debug_sel | w | 0 | 54 | 1 | unsigned | ||
scanner_debug_addr | w | 0 | 55 | 4 | unsigned | ||
U2_bitslip | w | 0 | 56 | 8 | unsigned | ||
U3_bitslip | w | 0 | 57 | 8 | unsigned | ||
adc_mmcm_psen | w | 0 | 58 | 2 | unsigned | ||
mmcm_reset | w | 0 | 59 | 1 | unsigned | ||
frequency_adc2 | r | 0 | 60 | 32 | unsigned | ||
phase_step_h | w | 0 | 61 | 20 | unsigned | ||
phase_step_l | w | 0 | 62 | 12 | unsigned | ||
modulo | w | 0 | 63 | 12 | unsigned | ||
ampi | w | 0 | 64 | 16 | unsigned | ||
ampq | w | 0 | 65 | 16 | unsigned | ||
dds_reset | w | 0 | 66 | 1 | unsigned | ||
rf_go | RF enable after interlocks are cleared | interlock | w | 0 | 67 | 1 | unsigned |
rf_status | r | 0 | 68 | 32 | unsigned | ||
pulse_boundary | w | 0 | 69 | 2 | unsigned | ||
mon_laser_sel | w | 0 | 70 | 1 | unsigned | ||
ch_keep | w | 0 | 71 | 12 | unsigned | ||
wave_samp_per | w | 0 | 72 | 8 | unsigned | ||
wave_shift | w | 0 | 73 | 3 | unsigned | ||
decay_samp_per | w | 0 | 74 | 8 | unsigned | ||
laser_samp_per | w | 0 | 75 | 8 | unsigned | ||
ddsa_modulo | Not used | rw | 0 | 76 | 12 | unsigned | |
ddsa_phstep_h | Offset for synthesizer clock multiplier | rw | 0 | 77 | 20 | unsigned | |
ddsa_phstep_l | Not used | rw | 0 | 78 | 12 | unsigned | |
rep_period | Seconds between output pulses | w | 0 | 79 | 28 | unsigned | |
pulse_length | Output pulse length in seconds | w | 0 | 80 | 24 | unsigned | |
source_re | Open loop DAC setting, real part | rw | 0 | 81 | 16 | unsigned | |
source_im | Open loop DAC setting, imaginary part | rw | 0 | 82 | 16 | unsigned | |
close_loop | 1 -> close I/Q loop with cavity probe | w | 0 | 83 | 1 | unsigned | |
monitor | w | 0 | 84 | 1 | unsigned | ||
ab_coeff | w | 0 | 85 | 16 | unsigned | ||
ext_trig_sel | w | 0 | 86 | 1 | unsigned | ||
inlk_mode_1 | w | 0 | 87 | 2 | unsigned | ||
inlk_mode_2 | w | 0 | 88 | 2 | unsigned | ||
inlk_mode_3 | w | 0 | 89 | 2 | unsigned | ||
inlk_mode_4 | w | 0 | 90 | 2 | unsigned | ||
reset_inlk_1 | w | 0 | 91 | 1 | unsigned | ||
reset_inlk_2 | w | 0 | 92 | 1 | unsigned | ||
reset_inlk_3 | w | 0 | 93 | 1 | unsigned | ||
reset_inlk_4 | w | 0 | 94 | 1 | unsigned | ||
thresh_noise | w | 0 | 95 | 16 | unsigned | ||
thresh_init | w | 0 | 96 | 16 | unsigned | ||
decay_coef | w | 0 | 97 | 16 | unsigned | ||
ddsb_modulo | w | 0 | 98 | 12 | unsigned | ||
ddsb_phstep_h | w | 0 | 99 | 20 | unsigned | ||
ddsb_phstep_l | w | 0 | 100 | 12 | unsigned | ||
adc1_max | r | 0 | 101 | 16 | unsigned | ||
adc2_max | r | 0 | 102 | 16 | unsigned | ||
adc3_max | r | 0 | 103 | 16 | unsigned | ||
adc4_max | r | 0 | 104 | 16 | unsigned | ||
adc1_min | r | 0 | 105 | 16 | unsigned | ||
adc2_min | r | 0 | 106 | 16 | unsigned | ||
adc3_min | r | 0 | 107 | 16 | unsigned | ||
adc4_min | r | 0 | 108 | 16 | unsigned | ||
slow_reset | w | 0 | 109 | 1 | unsigned | ||
v_thresh | w | 3 | 0x5000 | 16 | unsigned | ||
ramtest | rw | 3 | 0x02000 | 16 | unsigned | ||
scanner_mirror_val | r | 4 | 0x3000 | 7 | unsigned | ||
scanner | w | 4 | 0x4000 | 5 | unsigned | ||
banyan_data | r | 13 | 0x10000 | 32 | unsigned | ||
trace_data | r | 13 | 0x20000 | 16 | signed | ||
scanner_result_val | r | 11 | 0x130000 | 8 | unsigned |
