The tasks and questions below should be looked at as soon as possible since they might be blocking
Requirement | ePixUHR | SparkPix-S | SparkPix-ED |
---|---|---|---|
frame rate | 100kfps | 1Mfps | 1Mfps |
Power supplies | 2.5V Analog 1.3V (AS/DS/IO) | 2.5V Analog 1.3V (AS/DS/IO) 0.6V (Current sink!) | 1.3V (AS/DS/IO) |
Power for each supply | ePixUHR - 35 kHz | SparkPix-S: supply/ground and power consumption | t.b.d. |
Number of GT IOs per ASIC | 8 (outputs) | 8 (outputs) 1 clock in | t.b.d (The current agreement is to have 8 outputs) |
Expected I/O speed | 5.25 Gb/s | 5.25 Gb/s | 10 Gb/s |
Total data bandwidth | 42 Gbit/s | 42 Gbit/s | 80 Gbit/s |
There are three targeted cameras for this project:
2x2 ePix/SparkPix | 1M ePix | 2M SparkPix S | |||
Parameter (estimated) | Small Camera | Small Camera | Super tile | Super tile | Quad Camera |
Pixels | 129,024 px | 540,672 px | 967,680 | 1,161,216 px | 2,162,688 px |
Rate | 35kHz / 100kHz | 1MHz | 35kHz / 100kHz | 35kHz / 100kHz | 1MHz |
Focal Plane Area | 4cm x 4cm | 4cm x 4cm | 12cm x 10cm | 12cm x 12cm | 8cm x 8cm |
Front side footprint (window) | 5cm x 5cm | 5cm x 5cm | 14cm x 12cm | 14cm x 14cm | 10cm x 10cm |
Power (only ASIC) | 0.016 kW/??? | 0.021kW | 0.130 kW/??? | 0.144 kW/??? | 0.084 kW |
Weight | 1.5kg | 1.5kg | 9Kg | 10kg | 6kg |
Data volume | 56 Gbps/ 160 Gbps | 160 Gbps | 420 Gbps/ 1190 Gbps | 504 Gbps/ 1440 Gbps | 640 Gbps |
ASIC Power Requirement | Analog Section | Digital Section | 0.6V Sink | Analog TPS | ||||
---|---|---|---|---|---|---|---|---|
ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | |
Voltage | 1.3 V | 1.3V | 1.3V | 1.3V | ??? Maybe | 0.6 V | 2.5 V | 2.5V |
Required current | 10A (= 2.5 A* 4 ASIC) | 13.4 A (= 3.35A * 4 ASIC) | - With LVDS transceivers ???? | - With LVDS transceivers ???? | ??? (If existing lower or equal than SparkPixS) | -8 A | 0.4 A (=0.1 * 4) | 0.4 A (=0.1 * 4) |
System Requirement | +1.3 V @ +17.5 A (+30% current safety margin) | +1.3 V @ +3 A (+30% current safety margin) [waiting for the CML number] | +0.6 V @ -11 A (+30% current safety margin) | +2.5 V @ +0.5 A (+30% current safety margin) |
ePixUHR 140k 2x2 Detector Specs | ePixUHR 1.1M 6x6 Detector Specs | ePixUHR 1M 6x5 Detector Specs | SparkPix-S 500k 2x2 Detector Specs | SparkPix-S 2M 4x4 Detector Specs | KU15P (-A1156) Kintex Ultrascale+ FPGA USED IN ePixHR250M | KU15P (-E1517) Kintex Ultrascale+ | KU15P (-A1760) Kintex Ultrascale+ | XCVU160 (-C2104) Virtex Ultrascale | XCVU190 (-A2577) Virtex Ultrascale | VU13P (-A2577) Virtex Ultrascale+ | |
---|---|---|---|---|---|---|---|---|---|---|---|
General IO (HD, HP) | 48 HD, 486 HP | 96 HD, 416 HP | 96 HD, 416 HP | 52 HD, 364 HP | 0 HD, 448 HP | 0 HD, 448 HP | |||||
High Speed GTs (GTH/GTY) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceiver) Total: 48 High Speed GTs | - ASIC data: 288 = 8 lanes * 36 ASIC - Spare outputs : 0 - PGP communication: 72 = 12* 1.44 Tbps/ 275Gbps (6 Amphenol Transceivers) Total: 360 High Speed GTs | - ASIC data: 240 = 8 lanes * 30 ASIC - Spare outputs : 0 - PGP communication: 72 = 12 lanes * 1.19 Tbps/ 275Gbps (6 Amphenol Transceivers) Suggested 3 transceivers 1.4x compression in the detector Total: 312 High Speed GTs (If considering 5x2 Modules, 104 GTs each) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceivers) Total: 48 High Speed GTs | - ASIC data: 128 = 8 lanes * 16 ASIC - Spare outputs : 0 - PGP communication: 24* = 12* 495 Gbps/ 275Gbps (2 Amphenol Transceivers) Total: 152 High Speed GTs | 28 | 56 (32 GTH/24 GTY) | 76 (44 GTH/32 GTY) | 104 (52 GTH/52 GTY) | 120 (60 GTH/60 GTY) | 128 (0 GTH/128 GTY) |
Total Block RAM | 34.6 Mb | 34.6 Mb | 34.6 Mb | 115.2 Mb | 132.9 Mb | 94.5 Mb | |||||
UltraRam, HBM | 36 Mb, None | 36 Mb, None | 36 Mb, None | None, None | None, None | 360 Mb, None | |||||
Transceiver Speed (GTH, GTY) | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | GTH 16.3 Gb/s GTY 16.3 Gb/s Transceivers | GTH 16.3 Gb/s GTY 32.75 Gb/s Transceivers | GTH 16.3 Gb/s GTY 32.75 Gb/s Transceivers | GTH 16.3 Gb/s GTY 30.5 Gb/s Transceivers | GTH 16.3 Gb/s GTY 30.5 Gb/s Transceivers | GTY 32.75 Gb/s Transceivers |
Size | The PCB width is (preferably) 65 mm (2.56’’) | 35 x 35 mm | 40 x 40 mm | 42.5 x 42.5 mm | 47.5x47.5 mm | 52.5 x 52.5 mm | 52.5 x 52.5 mm | ||||
Cost | 5-9 k$ | 6-10k$ | 6-10 k$ | 40 k$ | 50-70 k$ | 60-110 k$ | |||||
Comments | The number of GTs in this FPGA does not fit any of the cameras we are targetting | This is fine for the 2x2 Systems. For the larger systems we need more than 3 FPGAs | This is fine for the 2x2 Systems. This is fine for the SparkPix-S 4x4 | This is fine for the 2x2 Systems. | This is fine for the 2x2 Systems (assuming we can fit the real estate). | This is fine for the 2x2 Systems.(assuming we can fit the real estate) |
*Done considering 1% Occupancy instead of maxing out the transceivers
UHR 2x2 | SparkPix S 2x2 | SparkPix S 4x4 | UHR 5x6 | UHR 6x6 | ||
---|---|---|---|---|---|---|
Requirements Characteristics | 48 GTs | 48 GTs | 152 GTs | 312 GTs | 360 GTs | |
KU15P (-A1156) Kintex U+ | 28 GTs / 352 mm2 / 10k$ | ❌ | ❌ | ❌ | ❌ | ❌ |
KU15P (-E1517) Kintex U+ | 56 GTs / 402 mm2 / 10k$ | ✅ | ✅ | ❌ | ❌ | ❌ |
KU15P (-A1760) Kintex U+ | 76 GTs / 42.52 mm2 / 10k$ | ✅ | ✅ | ✅ (2 FPGA) | ❌ | ❌ |
XCVU160 (-C2104) Virtex U | 104 GTs / 47.52 mm2 / 40k$ | ✅ | ✅ | ✅ (2 FPGA) | ✅ (1 FPGA/module) | ❌ |
XCVU190 (-A2577) Virtex U | 120 GTs / 47.52 mm2 / 70k$ | ✅ | ✅ | ✅(2 FPGA) | ✅ (1 FPGA/module) | ✅ (1 FPGA/module) |
VU13P (-A2577) Virtex U+ | 128 GTs / 52.52 mm2 / 110k$ | ✅ | ✅ | ✅(2 FPGA) | ✅ (1 FPGA/module) | ✅ (1 FPGA/module) |
Requirement | Parameters | Notes |
---|---|---|
Power supply | 24V consistent with the HR detector | |
Mechanical size | We would like to match the ePixHRM board dimensions to reuse cooling Side entrance detector
| |
Digital board | 2.56x5.265" | |
Power and communication | 2.56x5.240" | |
Carrier | 2.56x1.95" |
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Domain | Portion | Final Voltages | LDOs | DC/DC | DC/DC | ||||||
ANALOG | ASIC | G_AS_0 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS. The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W. If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W. The power drawn by the rest of analog voltages should be less than 2W. So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W. Considering the efficiency curves of the DC/DC converters: 34/85%/93% = 43W Total Analog Power | ||
G_AS_1 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | ||||||||
G_AS_2 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||
G_AS_3 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | ||||||||
G_VG_0 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +2.5V | LT3086 (LDO) Max 2.1A | ← +3V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (>90% efficiency for this loads) | ← +6 V | ||||
G_VG_1 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | |||||||||
G_VG_2 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +6 V | ||||||||
G_VG_3 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | |||||||||
G_AS_2V5 2.5V @ <0.5 A | ← +2.5V | ||||||||||
DIGITAL | ASIC | G_DS_0 1.3V @3A | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V For the digital consumption of the ASIC we do not have precise numbers regarding the new CML logic. Let's assume a double consumption w.r.t the LVDS design. 1.3V*6A = 8W LDO losses = 0.5*6A = 3W 11W / 85% / 93% = 14W(ASIC Digital) Regarding the FPGA considering a worst case efficiency of the DC/DC: Worst case scenario, the remaining electronics will draw 1A, multiplied by 5.5V = 5.5W, which before the DCDC will become 5.5W /85 = 7W 42.5W Total Digital Power | ||
G_DS_X 1.3V @???A (CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | ||||||||
G_IO_0 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||
G_IO_X 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | ||||||||
FPGA | VCCINT 0.85V @7.05 A | ← +0.85V | LMZ31530 30 A (Around 90% efficiency) | ← +6 V | |||||||
VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX 1.8V @0.7A | ← +1.8V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||||
MGTAVCC +MGTYAVCC 0.9V @3.7A | ← +0.9V | ||||||||||
VCC_1.2V + MGTAVTT + MGTYAVTT 1.2V @5.5A | ← +1.2V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (Between 80 and 90 efficiency) | ← +6 V | ||||||||
DAC/ADC/Misc | VDD_5V +5V @ <1A | ← 5V | LT3086 (LDO) Max 2.1A | ← +5.5V (TBD) | |||||||
VDD_3V3 +3.3V @ <1A | ← +3.3V | LT3086 (LDO) Max 2.1A | |||||||||
VDD_1V8 +1.8V @ <1A | ← +1.8V | LT3086 (LDO) Max 2.1A | |||||||||
85.5W Total Power (Estimation without CML transceivers) |
Component | Product number | Quantity | Input Voltage | Output Voltage | Max Current | Comment |
DC/DC Step Down converter | LT8648S | 4 | 3V to 42V | 0.6V to 42V | 15A | |
DC/DC PMIC | TPSM5D1806 | 7 | 4.5V to 15V | 0.5V to 5.5V | Dual 6A / Single 12A | |
DC/DC Buck converter | LMZ31530 | 1 | 3V to 14.5V | 0.6V to 3.6V | 30A | Not in stock, replace with TPSM846C24? Other option is TPS53355 that is the IC used inside of LMZ31530. |
Low Noise LDO | LT1764 | 8 | 2.7V to 20V | 1.21V to 20V | 3A | Low Output Noise: 40µVRMS (10Hz to 100kHz) |
LDO alternative to LT1764 | LT3083 | 8 | 1.2V to 23V | Adjustable to 0V | 3A | Low Output Noise: 40μVRMS (10Hz to 100kHz) |
Low Noise LDO | LT3086 | 12 | 1.4V to 40V | 0.4V to 32V | 2.1A | Low Output Noise: 40µVRMS (10Hz to 100kHz) |
Negative Linear Regulator | LT3091 | 8 | –1.5V to –36V | 0V to –32V | -1.5A | Low Output Noise: 18µVRMS (10Hz to 100kHz) |
Functionality | IO type | Quantity | switching specification |
---|---|---|---|
ASIC control (GR, ...) | 2.5V SE | Static | |
SUGOI | |||
SACI | |||
DATA | CLM? | 40 + spares? | 10Gbps |
System IO | |||
transceiver | 25Gbps | ||
supporting electronics | |||
enablels for power | |||
Slow ADC (current and voltage monitors, temperature sensors...) | |||
HS ADC | |||
serial number | |||
HS DAC | |||
Lower priority needs (R&D on system) | |||
FPGA to FPGA interconnection | requires GT+specific connector |
Functionality | IO type | Quantity | Observations |
---|---|---|---|
Carrier to analog board | 1 |
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Analog to digital board | 1 | ||
External power supply | 1 |
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The components listed in the expansion box below are currently missing from the SLAC Altium library located on OneDrive (Altium_Yee_lib).
The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.
UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575)
The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.
The carrier board contains the specific ASICs and any passive components that are needed.