Introduction

The ePixHR5kHz is one of the first in-house LCLS-II detectors in development and is targeted at being a replacement for the ePix10ka, with the capability to run data 5kHz frame rate. The prototype has been built within the mechanical envelope of a front-facing small ePix10k as can be seen in Figure 1.


Figure 1. Image of the ePixHR prototype camera.


A single ASIC (v2) has been attached to the carrier board and a small sensor (48x48 pixels). The sensor has a standard entrance window, i.e., not the thin entrance window intended for the final detectors. The requirements that the detector was designed for and the measured results stated by TID for (Matrix+ADC) can be seen below:


Table 1. Design requirements and measured performance of key characteristics.


Requirements

Results

Mode of Operation

Integrating with:

•auto-ranging high-low

•auto-ranging medium-low

•fixed high gain

•fixed medium gain

•fixed low gain

Integrating with:

•auto-ranging high-low

•auto-ranging medium-low

•fixed high gain

•fixed medium gain

•fixed low gain

Pixel size

100x100 µm2

100x100 µm2

Range

Auto-ranging: >40000 keV 

(transitions 400keV/1200keV selectable)

Fixed high gain: >400 keV 

Fixed medium gain >1200keV

Fixed low gain: >40000 keV

Auto-ranging: 64000 keV

(transitions 400keV/1200keV selectable and tunable)

Fixed high gain: 880 keV 

Fixed medium gain 2640keV

Fixed low gain: 64,000 keV

Noise r.m.s.

< ~400eV

(~110e-rms)

~ 270eV*

(~75e-rms)*


Gain modes

As stated in Table 1., the detector has a 100um pixel pitch and can be configured in 5 different gain modes; 3 fixed gain modes and 2 auto-ranging gain modes. In the same way as for the ePix10k ASIC, the gain mode is selected using the tr_bit register and the pixel map settings. The combinations to get to the specific gain modes can be seen in table 3.


Table 2. Tr_bit and pixel config file combinations are required to get a specific gain mode.

Gain mode

Tr_bit value

Pixel config file

FH

1

12

FM

0

12

FL

Does not matter

8

AHL

1

0

AML

0

0

AHL-L

1

4

AML-L

0

4


Readout channel, timing diagram, and targeted machine rates

As with the other members of the ePix family of detectors, the analog chain consists of a CSA with a switched reset scheme, a 1st order low pass filter, and a correlated double sampler. The pixel array size for the ASIC is 192x144, however, since only a small sensor is used for the prototype, only 48x48 pixels are bonded to a sensor.

Figure 3. Analogue channel layout for the ePixHR5kHz pixel.

In the initial testing of this camera, the firmware used a single trigger scheme to read out the events. Due to resulting baseline instability, this was changed to a dual trigger system, where the DAQ trigger controls at what frequency the frames are read out, and the Run trigger decided at what frequency the ASIC is being run. As such, if the run trigger is set to 5kHz, and the DAQ trigger to 120Hz, then we only read out an event every 8ms. The idea is to have the ASIC always run at a set frame rate, to ensure thermal (baseline) stability, while we can change the readout rate to match the pulse arrival frequency of the beam. We still need to verify that the new trigger scheme works. The timing diagram for the readout of the ePixHR5kHz ASIC can be seen in Figure 4.


Figure 4. The timing diagram for the pixel readout for the ePixHR5kHz.

The trigger arrival (run trigger) is located at the starting point on the left. Both the R0delay and ACQ delay are tied back to the trigger. The R0delay gives the time from the trigger arriving until the CSA is taken out of reset and starts integrating the charge from the sensor. The ACQdelay gives the time from the trigger until the ACQ goes high and the first sampling of the CDS takes place. The second CDS sampling takes place at the end of the ACQ window. As such, the RO window, also referred to as the baseline integration is set by ACQdelay-R0delay, while the ACQ window, also referred to as the signal integration, is set by the ACQwidth. The ACQWidth starts from the end of the ACQ delay. The SROdelay sets the time from the end of the ACQ window until the readout starts. Once the SRO signal goes high, the readout starts and the conversion time needed fully read out the collected values is dictated by the number of rows the ADC is reading out, and the SERDES clocking frequency used, as described here. The additional time needed in this readout scheme to reset the channel (CSA and CDS) is yet to be experimentally determined but is currently assumed to be in the 3-4 us range. All the registers in the GUI are stated as units of 10ns. As such, setting ACQwidth to 2400 gives an ACQ (signal) integration window of 24 us.


The detector is aimed at handling the readout rates set by “5kHz” machine operation. The actual rep rates that the machine will be operated at can be seen on the left (table provided by Lorenzo). The four highest frame rates are: 3714 Hz; 4464 Hz; 4642 Hz; and 5102 Hz.

Figure 5. Machine operation rep rates and targeted detectors.

Add section on running Run and DAQ triggers differently or the same:

The machine base rates, and the resulting frequencies that can be hit if the Run trigger is kept set when changing the DAQ trigger, can be seen in the Excel file below.

Allowed ACQ trigger rates for set Run trigger rate LCLS-II


Quantum Efficiency

For the prototype detector, a small 500 um thick Si sensor was used with the standard entrance window (1um Al, 1 um non-sensitive Si) was used. For the final detector, a full-size 500 um thick Si sensor with a thin entrance window (Sintef - 100nm Al, 100nm non-sensitive Si) will be used. A first-order estimate of the resulting detection efficiency as a function of photon energy for the two types of sensors can be seen in Figure 6. It should be noted that the non-sensitive region and the Al thickness have not been measured and are best estimates. For the plots stating "with shield" the detection efficiency has been calculated assuming a 25 um thick Polyimide shield located in front of the sensor. An excel sheet containing the values for both sensors can be found under the Figure.


Figure 6. First-order estimate for the detection efficiency for the standard sensor and the thin entrance window sensor.

QE ePixHR - thin entrance window and standard.xlsx


Initial testing

Gains

A first evaluation of the gains for the high and low gains, as well as the ratio between the two, can be seen in Table 3, while figure 7 show the gain maps (fitted peal position for 22.1 keV photons). It should be noted that this was measured using v2 of the ASIC, the original single trigger firmware, 262MHz Serdes clock, symmetrical ACQ/RO widths (24us), and a 4kHz frame rate. This measurement has to be redone and validated for v4 of the ASIC, with the final settings and firmware.


Table 3. Initial measurements for the FH and FM gains.

Gain mode (median)gain estimate
FH27.75 eV/ADU
FM76.15 eV/ADU
Ratio FM/FH0.364


Figure 7. Pixel map and histograms for the fitted peal position (Ag fluorescence - 22.1 keV), and the gain ratio map.

Pedestals

The pedestals shown below in figure 8 and summarised in Table 4, were taken under the same detector settings as the gain maps.


Table 4. Pedestal values observed for the different gain modes.

Gain mode

Pedestal median (ADU)

Pedestal sigma (ADU)

FH

10,485

149

FM

10,110

149

FL

9,897

150

AHL

10,487

148

AML

10,114

149



Figure 8. Pedestal distributions and maps for the ePixHR5kHz detector.


Noise

The noise shown below in figure 9 and summarised in Table 5, were taken under the same detector settings as the gain maps.

Table 5. Noise values observed for the different gain modes.

Gain mode

Noise median (ADU)

Noise sigma (ADU)

Noise median (e-)

FH

15.31

1.02

118

FM

8.49

1.03

180

FL

6.24

1.11

-------

AHL

17.02

1.08

131

AML

9.13

1.11

191




Figure 9. Pedestal distributions and maps for the ePixHR5kHz detector.




















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