Firmware
| Task | Description | Status | Date | Owner |
|---|---|---|---|---|
| AxiLiteCrossbar | Create a xbar for the ASICTOP module | done | Dawood | |
| Port ASIC control module | use Register control as copy and paste into the new module | done | Dawood | |
| Port trigger module | copy from epix-hr-single-10k | done | Dawood | |
| Simulate | Simulate both modules | done | Dawood | |
| axilite address space | Define address space for the ASIC top | started | Dawood | |
| axiStreamRepeaters | Repeaters for the timing information (x5) | Done |
| Dawood |
| axiStreamBatcher | Creates the data package with image and timing info (x5) | Done |
| Dawood |
| DigitalAsicStreamV2 | Port to 2m and increase number of ASICs to 4 | Done |
| Dawood |
| Synthesis | Make sure design synthesizes completed, update constraints if needed. | Done |
| Dawood |
| Software | Complete companion device/register definition, if missing. | Done |
| Dawood |
| ASIC Model | Port from simulation test bench an ASIC model to a new HDL entity that will mimic the ASIC data path. Needs a data length counter to send one frame per SRO. Map all IO to the ASIC even though some will not be used for this simulation. | Done |
| Dawood |
| DigitalAsicSttreamV3 | Create internal module to de-interleave the images | Dawood | ||
| Hardware deployment | Test HW/SW register access | Done |
| Dawood/Dionisio |
| Chip scope pro | Integrate chip scope pro | Dionisio | ||
| Voltage source test | enable sources and check test points/capacitors for all channels |
| Dawood | |
| Slow ADC test | Test current, temperature and humidity | Done | Julian | |
| Fast ADC test | Done | Julian | ||
| Add serial number and test | Started | Julian | ||
| DAC test | apply DAC value and check test points | Dawood | ||
| SI5345 Jitter cleaner | Generate file and have software write it to jitter cleaner | Dawood |
Software
| Task | Description | Status | Owner | |
|---|---|---|---|---|
| top level structure | Create top level | Done |
| Dionisio |
| Add devices ASIC control and trigger | Copy from epix-hr-single-10k, add new addresses | Done |
| Dawood |
| Viewer | Discuss with Ben to find out if we should use the new ePix viewr | Dawood/Ben | ||
Test setup
| Task | Description | Status | Owner |
|---|---|---|---|
| FW/SW data verification | Fake data generation and display | ||
| Check waveforms in HW | Using TTL outputs | ||
| Check SACI waveforms | Using analog test points | ||
| Check power enable | Using test points or analog board | ||
| Check timing receiver | Use timing board from Matt | ||
Current test status
| Module | Description | Simulation | Test in hardware |
|---|---|---|---|
| RegisterControlDualClock | VR2 (6V EN), VR3 (1.8V), VR4 (3.3V DIG) | Tested waveform to ASICs and AXILite RW | Tested multiplexer to digital output, analog and digital serial ID, AXILite RW |
| TrigControlAxi | Tested software trigger to generate waveforms to ASICs | ||
| AXiStreamRepeater | Not tested | ||
| DigitalAsicStreamAxiV2 | Not tested | ||
| AxiStreamBatcherEventBuilder | Not tested | ||
| AxiLiteSaciMaster | U22/U20/U21 (level shifters) | Testing Saci reads and writes with ASICs | |
| AppClk | - | ||
| AppDeser | Not tested | ||
| PwrCtrl | Tested 6V, analog and digital enable with testpoints | ||
| DAC - Max5443 | U12/U16 (level shifter), U79 (DAC) | Tested with testpoint | |
| DAC - DacWaveformGenAxi | U76/U77/U75 | Tested waveform | Tested with testpoint single writes |
| AdcMon | U5 (Slow ADC - DIG) U10/U12/U14(Slow ADCs AN) | ||
| TimingRx | - | ||
| Chip scope pro | error after loading bit stream | ||
| SI5345 Jitter cleaner | Partially tested. Pending FPGA modifications to eliminate lol dependency | Device ID registers seem to be readable. Logic in FPGA still depend on lol output, so AXI locks after configuring. | |
| PROM | U13 (PROM) | Boot from PROM | |
| JTAG | J2 | Tested by writing bitstream | |
| Clock splitter | U60/U59/U61 | ||
| ASIC lanes |
Overview
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