Introduction
The continued desire for x-ray pixel detectors with higher frame rates will stress the ability of detector developers to provide sufficient off-chip bandwidth to reach continuous frame rates in the megahertz regime. A continuous 1 MHz detector with merely 256 x 256 pixels at 16-bit resolution, for example, will require 1,000 Gbps (i.e., 1 Tbps) bandwidth off the chip. It is impractical to have multiple high-speed transceivers running in parallel to provide such bandwidth, and this aspect represents the first data bottleneck. Today, most x-ray pixel detector ASICs have been used mainly for analog signal processing of the charge from the sensor layer and the transmission of raw pixel data off the detector ASIC. With the availability of more advanced ASIC technology nodes for scientific application, more digital functionality from the computing domains (e.g., compression) can be integrated directly into the detector ASIC to increase data velocity. However, these computing functionalities often have high and variable latency, whereas scientific detectors must operate in real-time (i.e., stall-free) to support continuous streaming of sampled data. In this proposal, we pursue new approaches to reduce the data size by performing data compression directly on a detector ASIC in a streaming manner before sending it off-chip. In this manner, we will make the most efficient use of the off-chip bandwidth and thus maximize detector frame rates.
High level specifications
- Prototype One
- 48 x 48 pixel Array
- Frame rate
- 100kfps when compressing data or performing ROI
- 35Kfps uncompressed data
- Programable memory to download dark subtraction
- Compression modes
- Lossless
- Applied to all data above the minimum threshold
- TBD
- Lossy
- Poisson encoding...
- TBD
- Uncompressed data
- In this mode the matrix data is sent directly to the output streams via the priority encoder FIFOs
- Lossless
- Number of data streams : 2
- The number of ASIC streaming output will be two. This keeps the design simple but also allows the internal building blocks and data receiver to send/receive data over multiple links which will be the case of a full reticle size detector.
CoSimulation approach
ASIC documentation
(SparkPix-RT ASIC Documentation)
Curated datasets
Repo
- Compression
- ASIC
- CoSimulation
PCB Designs
Analog Board: PC_261_100_76_C00
Digital Board: PC_261_100_77_C00
Carrier Board 48x48 Prototype: 23pc012 - SparkPixRT 48x48 Carrier Board
Test system and test results
231002 - SparkPixRT - First Results.pptx
231004 - SparkPixRT - How to run the SparkPixRT camera.pptx
231005 - SparkPixRT - First Look at Compressed Data.pptx
Scripts
RT_frame_reader.py
uncompressed_data_pixnummodeEn.dat
dark_memory_programmed_incrementally.dat
Reports
Published papers
Huang, Panpan, et al. "Fast digital lossy compression for X-ray ptychographic data." Journal of synchrotron radiation 28.1 (2021): 292-300. https://journals.iucr.org/s/issues/2021/01/00/gy5014/index.html
Strempfer, Sebastian, et al. "Designing a streaming data coalescing architecture for scientific detector ASICs with variable data velocity." 2021 3rd Annual Workshop on Extreme-scale Experiment-in-the-Loop Computing (XLOOP). IEEE, 2021. https://ieeexplore.ieee.org/abstract/document/9652802
Strempfer, Sebastian, et al. "A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging." Journal of Instrumentation 17.10 (2022): P10042. https://iopscience.iop.org/article/10.1088/1748-0221/17/10/P10042/meta
TBD
NSS contributions