Source code can be found here and can be run locally using Local PyDM/Simulacrum Setup
GUI Procedure
Piezo Pre-RF Check
SSA Characterization
Cavity Tuning
- Enable the piezo (set ACCL:LXB:XXXX:PZT:ENABLE to 1)
- While it doesn't enable (while ACCL:LXB:XXXX:PZT:ENABLESTAT is not 1), toggle ENABLE to disabled (0) and enabled (1) again
- Set the piezo to manual (set ACCL:LXB:XXXX:PZT:MODECTRL to 0)
- While it doesn't enable (while ACCL:LXB:XXXX:PZT:MODESTAT is not 0), toggle MODECTRL to feedback (1) and manual (0) again
- Set the DC voltage offset (ACCL:LXB:XXXX:PZT:DAC_SP) to 0
- Set the bias voltage (ACCL:LXB:XXXX:PZT:BIAS) to 25
- Set the cavity drive level (ACCL:LXB:XXXX:SEL_ASET) to 15
- Set the RF to chirp (set ACCL:LXB:XXXX:RFMODECTRL to 5)
- Turn on SSA (set ACCL:LXB:XXXX:SSA:PowerOn to 1)
- Wait for SSA to turn on (wait until ACCL:LXB:XXXX:SSA:StatusMsg is 3)
- Reset cavity interlocks (set ACCL:LXB:XXXX:INTLK_RESET_ALL to 1) and wait 3s
- If the reset failed (ACCL:LXB:XXXX:RFPERMIT is 0)
- Retry up to 2 more times
- If the reset succeed within 3 total attemps
- Continue to step 9.b.i
- If the reset fails after 3 total attempts
- Throw an error
- If the reset succeeded (ACCL:LXB:XXXX:RFPERMIT is not 0)
- If the cavity isn't online (if ACCL:LXB:XXXX:HWMODE is not 0)
- Throw an error
- If the cavity is online (if ACCL:LXB:XXXX:HWMODE is 0)
- Turn on the RF (set ACCL:LXB:XXXX:RFCTRL to 1)
- Wait for the RF to turn on (wait while ACCL:LXB:XXXX:RFSTATE is not 1)
- If the cavity isn't online (if ACCL:LXB:XXXX:HWMODE is not 0)
- If the reset failed (ACCL:LXB:XXXX:RFPERMIT is 0)