As mentioned in the previous slide, the ADC readout time is set by the Serdes clock and the number of pixels each ADC handles. The readout time as a function of different Serdes clockings can be seen in the table on the left (provided by Lorenzo).
Table.1 Frequencies, integration times, and frame-rates.
The Serdes clock is divided down by five to create the ADC clock. The ADC sampling period is then given by dividing the ADC clk with the over sampling ratio (OSR). The readout time is then given by the ADC sampling period times the number of pixels the ADC have to read out (146).
The maximum frame rate available for a set Serdes clocking can then be calculated by adding the ACQdelay value, the ACQwidth, the SROdelay, the ADC readout time and the additional reset period time needed to get the period length of one readout cycle.
The Serdes clock to maximum frame rate seen in the two plots below (for an asymmetric and symmetric configuration of the baseline and signal integration periods) Has been produced using a small Matlab script called Maximum_frame_rate_ePixHR.m (available from Conny).
Figure 1. Maximum frame rate as a function of Serdes clock and R0/ACQ window widths.