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ASIC level requirements summary

RequirementePixUHRSparkPix-SSparkPix-ED (question)
frame rate100kfps1Mfps1Mfps
Power supplies

2.5V Analog

1.3V (AS/DS/IO)

2.5V Analog

1.3V (AS/DS/IO)

0.6V (Current sink!)

1.2V (AS/DS/IO)
Power for each supplyePixUHR - 35 kHzSparkPix-S: supply/ground and power consumptiont.b.d.
Number of GT IOs per ASIC

8 (outputs)
1 clock in

8 (outputs)
1 clock in		t.b.d
Expected I/O speed5.25 Gb/s5.25 Gb/s10 Gb/s (question)

Total data bandwidth

42 Gbit/s38 Gbit/s(question)




Parameter

(estimated)

Small Camera 

ePixHR/UHR – 140k

2 x 2 ASIC

Super tile

ePixHR/UHR – 1M

6 x 6 ASIC

Small Camera 

SparkPix S – 500k

2 x 2 ASIC

Quad Camera 

SparkPix S – 2M

4 x 4 ASIC

Pixels

129,024 px

(168 *192*4)

1,161,216 px

(168 *192*36)

540,672 px

(352*384*4)

2,162,688 px

(352*384*16)

Rate

35kHz / 100kHz

35kHz / 100kHz

1MHz

1MHz

Area

5cm x 5cm

14cm x 14cm

5cm x 5cm

14cm x 14cm

Power 

0.06kW / 0.15kW

0.3kW / 0.9kW

0.5kW

2.0kW

Weight

1.5kg

10kg

1.5kg

6kg

Data volume 

56 Gbps/ 160 Gbps

504 Gbps/ 1440 Gbps

160 Gbps

640 Gbps

From ASIC to FPGA

168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame

@35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps

@100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps

From FPGA to PC

168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame

@32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps

@140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps

@1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps

@4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps

@16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps


FPGA Selection


ePixUHR 140k

2x2 Detector

Specs

ePixUHR 1M

6x6 Detector

Specs

SparkPix-S 500k

2x2 Detector

Specs

SparkPix-S 2M

4x4 Detector

Specs

XCVU160 (-C2104)

Virtex Ultrascale

XCVU190 (-A2577)

Virtex Ultrascale

KU15P (-A1760)

Kintex Ultrascale+

VU13P (-A2577)

Virtex Ultrascale+

General IO (HD, HP)





52 HD, 364 HP

0 HD, 448 HP

96 HD, 416 HP

0 HD, 448 HP

High Speed IO (GTH/GTY)

- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbps/ 275Gbps

(1 Amphenol Transceiver)

Total:

48 High Speed IOs

- ASIC data:

288 = 8 lanes * 36 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12* 1.44 Tbps/ 275Gbps

(6 Amphenol Transceivers)

Total:

360 High Speed IOs

- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbps/ 275Gbps

(3 Amphenol Transceivers)

Total:

48 High Speed IOs

- ASIC data:

128 = 8 lanes * 16 ASIC

- Spare outputs :

0

- PGP communication:

24* = 12* 495 Gbps/ 275Gbps

(2 Amphenol Transceivers)

Total:

152 High Speed IOs

104

(52 GTH/52 GTY)

120

(60 GTH/60 GTY)

76

(44 GTH/32 GTY)

128

(0 GTH/128 GTY)

Total Block RAM





115.2 Mb

132.9 Mb

34.6 Mb

94.5 Mb

UltraRam, HBM





None, None

None, None

36 Mb, None

360 Mb, None

Transceiver Speed

 (GTH, GTY)

> 10 Gbps

> 10 Gbps

> 10 Gbps

> 10 Gbps

GTH 16.3Gb/s

GTY 30.5Gb/s

Transceivers

GTH 16.3Gb/s

GTY 30.5Gb/s

Transceivers

GTH 16.3Gb/s

GTY 32.75Gb/s

Transceivers

GTY 32.75Gb/s

Transceivers

Size

The PCB width is (preferably) 65 mm (2.56’’)




47.5x47.5 mm

52.5 x 52.5 mm

42.5 x 42.5 mm

52.5 x 52.5 mm

Cost





40 k$

50-70 k$

6-10 k$

60-110 k$

*Done considering 1% Occupancy instead of maxing out the transceivers


ePixUHR 140k 2x2 Detector System

ePixUHR 1M 6x6 Detector System

SparkPix S – 500k 2 x 2 ASIC Detector System

SparkPix S 2M 4x4 Detector System



System level

RequirementParameters

Power supply24V consistent with the HR detector

Mechanical size

We would like to match the ePixHRM board dimensions to reuse cooling

Side entrance detector

  • Existing 75x175mmx58:
  • max envelope would be (100x175x75mm)


Digital board2.56x5.265"

Power and communication2.56x5.240"

Carrier

2.56x1.95


Can we do it smaller?

What is the minimum amount of components that need to leave in this board











ePixUHR Signals (single ASIC)

N# Pins


Power Digital Signals

N# Pins


Digital Core Signals

N# Pins


P&CB Signals

N# Pins

Waveform/ ASIC Ctrl

5


LDO enables

7


Env. Monitors

7


Misce

24

Clk

2 (0 if also clk_matrix is sent via GT)


DCDC Syncs

2


Bias DAC

4


Spare

6

Slow Ctrl (SACI/Sugoi)

4





HS DAC

4




Digital Monitor

2





HS ADC

6+24+8 =38










Miscellan

5










Jitter Cleaner

12




Total

13


Total

9


Total

70


Total

30


TOTAL = 13 * 4(n.Asics) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP

Resources used: 32+12 = 44 GTH

Discarding the extra 4 spares we can only use GTH signals, without the requirement of separate MGTY supplies.

Even if we run the Amphenol Transceivers at the GTH speed (16.3Gbps), one transceiver gives us 179 Gbps (16.3 Gbps * 11 lanes) of bandwidth, which is enough for the 160Gbps expected by the 2x2 detector

Component

Product number

Operation Voltage

Power consumption

N# I/O needed

Needs substitution?

Quad SPI Configuration Memory

MT25QU01GBBB8E12

1.8 V

Max 50 mA

4

No, we can use HR pins

JTAG


1.8/1.5/1.2 V


4

No, we can either use HR or go to 1.2V

Analog Monitor (SlowADC) ADC

ADS1217

AVDD =3V, DVDD =1.8V

< 1 mA

7

Maybe. The datasheet guarantees operation for digital down to 2.7V,  in HR250 was put at 1.8. Check if it is fine!

Analog Monitor MUX (x5)

MAX4734

AVDD =3V

< 1 uA

None

They are controlled by the ADC

Humidity sensor

HIH_5031_001

3 V


None

No

Thermistor

NTC_NHQM103B375T10



None

No

Oscillators

•371 MHz XLL726371.428571I

•156 MHz 536FB156M250DG

•48 MHz CX3225SB48000D0FPJC1

2.5 V



Both 1.8 V and 2.5V solutions can be found depending on the voltage we want to use

Clock Fanout

SI53340-B-GM

2.5 / 1.8V



Now is 2.5, probably can be switch to 1.8, but since its AC-coupled should not matter. Check if we can remove the 2.5 LDO

Clock Jitter cleaner

SI5345_64QFN

VDD = 3.3V, DVDD =1.8V


12 + n. clks


Programmable Oscillator

LMK61E2

3.3 V



Used?


High Speed ADC

AD9249

1.8 V

Max 58mW/channel:

58*12 = 700mW

38

No

ADC_MON_VCM Buffer

AD8607_MSO8

1.8V




Bias DAC (HV Ring)

MAX5443 (DAC) +

MAX14611 (Level Shifter) +

REF192GS  (Voltage reference)

3.0 V (VCCA)


4

Maybe? Will the sensors have an HV ring?

ASIC clk fanout

SI53340-B-GM




Probably not needed

HS DAC (Vcalib_p)

MAX5719A(DAC)+

MAX14611 (Level Shifter) +

OP213 (Buffer)

MAX6126A41+(Vref)

5V



Why was this chosen? Do we need the 5 V supply?

Level Shifter for Power controllers

MAX3378EETD (x2)

MAX3373E_SOT23_8 (x1)

1.8V -> 3.3V




Serial number

DS2411R

1.8V


















IO

For single ended → check the electrical specification


System level accounting

FunctionalityIO typeQuantityswitching specification
ASIC control (GR, ...)2.5V SE
Static
SUGOI


SACI






DATACLM?40 + spares?10Gbps




System IO


transceiver

25Gbps

supporting electronics




enablels for power


Slow ADC (current and voltage monitors, temperature sensors...)


HS ADC


serial number




HS DAC














Lower priority needs (R&D on system)


FPGA to FPGA interconnection

requires GT+specific connector








Goal is to have a decision on the FPGA package and family.

Kintex Ultrascale+ vs Virtex?


Transceiver

Ideal is to reuse the 300Gbps Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode power supply.


Board material 

Needs to be FR408HR or better


System level simulation 

GT to the ASICs

GT to the transceivers

Power drops


Connectors

FunctionalityIO typeQuantityObservations
carrier to digital board
1Can we use smaller connectors since the number of data IOs per ASIC reduces from 24 to 10?
Digital to Power and communication
1
Power communication to external power supply
1



Notes:

  • FPGA intercommunication
  • co-design with the data reduction pipeline
  • DFX for streaming pre-processing and eventually microAI, reusable building blocks



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