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Source code can be found here and can be run locally using Local PyDM/Simulacrum Setup

GUI Procedure

Piezo Pre-RF Check

Piezo Pre-RF Check

SSA Characterization

SSA Characterization

Cavity Tuning

cavity tuning

  1. Enable the piezo (set ACCL:LXB:XXXX:PZT:ENABLE to 1)
    1. While it doesn't enable (while ACCL:LXB:XXXX:PZT:ENABLESTAT is not 1), toggle ENABLE to disabled (0) and enabled (1) again
  2. Set the piezo to manual (set ACCL:LXB:XXXX:PZT:MODECTRL to 0)
    1. While it doesn't enable (while ACCL:LXB:XXXX:PZT:MODESTAT is not 0), toggle MODECTRL to feedback (1) and manual (0) again
  3. Set the DC voltage offset (ACCL:LXB:XXXX:PZT:DAC_SP) to 0
  4. Set the bias voltage (ACCL:LXB:XXXX:PZT:BIAS) to 25
  5. Set the cavity drive level (ACCL:LXB:XXXX:SEL_ASET) to 15
  6. Set the RF to chirp (set ACCL:LXB:XXXX:RFMODECTRL to 5)
  7. Turn on SSA (set ACCL:LXB:XXXX:SSA:PowerOn to 1)
  8. Wait for SSA to turn on (wait until ACCL:LXB:XXXX:SSA:StatusMsg is 3)
  9. Reset cavity interlocks (set ACCL:LXB:XXXX:INTLK_RESET_ALL to 1) and wait 3s
    1. If the reset failed (ACCL:LXB:XXXX:RFPERMIT is 0)
      1. Retry up to 2 more times
      2. If the reset succeed within 3 total attemps
        1. Continue to step 9.b.i
      3. If the reset fails after 3 total attempts
        1. Throw an error
    2. If the reset succeeded (ACCL:LXB:XXXX:RFPERMIT is not 0)
      1. If the cavity isn't online (if ACCL:LXB:XXXX:HWMODE is not 0)
        1. Throw an error
      2. If the cavity is online (if ACCL:LXB:XXXX:HWMODE is 0)
        1. Turn on the RF (set ACCL:LXB:XXXX:RFCTRL to 1)
        2. Wait for the RF to turn on (wait while ACCL:LXB:XXXX:RFSTATE is not 1)
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