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  • for user-supplied devices that are not integrated with the DAQ we will provide a TTL trigger and a network-based timestamp
  • this will be done using a TPR (PC_260_101_04_C02) (https://github.com/slaclab/evr-card-g2) (which only receives L1Accepts, not transitions)
  • the first example of this will be for the timepix detector in RIX in second week Oct. 2021:
    • Chris F. will take the lead on this
    • a machine with TPR will be placed in the rack that has the andor (rack 4?) where we can patch a TTL trigger to the beamline
    • timestamps can be retrieved analogous to this app (https://github.com/slac-lcls/lcls2/blob/master/psdaq/psdaq/app/pvcam.cc)
    • this machine can be a clone of the andor machine, but I think we need tpr-firmware instead of evr-firmware (to be confirmed with Matt)
    • the TPR also needs a standard 12-BNC breakout cable to provide the TTL triggers
    • we will meet with Anton Tremsin to discuss the trigger/network xface
    • this machine could perhaps be reused for RIXCCD so it could use a 10Gb DRP interface.  This could also be used to startup processes with procmgr.

Meeting Notes

9/9/2021 – MCP/Timepix Meeting with Anton Tremsin

  • The Timepix detector is incapable of receiving timestamp information over a network interface. Thus, some other mechanism will be needed to synchronize the timestamps of the Timepix detector and the LCLS DAQ system.
  • The Timepix detector requires two TTL inputs: Reset and Trigger.   The Reset signal must precede the first Trigger signal.
  • The LCLS DAQ developers believe that this Reset+Trigger interface can be integrated successfully for a trigger rate of 120 Hz, which is the short-term goal.
  • When and if the Timepix detector is chosen for integration at trigger rates greater than 120 Hz, hardware integration with the LCLS DAQ timestamp will be required.


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